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M50FW080 数据表(PDF) 40 Page - STMicroelectronics |
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M50FW080 数据表(HTML) 40 Page - STMicroelectronics |
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40 / 56 page ![]() DC and AC parameters M50FW080 40/55 Figure 10. FWH interface clock waveform Table 21. FWH interface clock characteristics Symbol Parameter Test Condition Value Unit tCYC CLK Cycle Time(1) 1. Devices on the PCI Bus must work with any clock frequency between DC and 33MHz. Below 16MHz devices may be guaranteed by design rather than tested. Refer to PCI Specification. Min 30 ns tHIGH CLK High Time Min 11 ns tLOW CLK Low Time Min 11 ns CLK Slew Rate peak to peak Min 1 V/ns Max 4 V/ns AI03403 tHIGH tLOW 0.6 VCC tCYC 0.5 VCC 0.4 VCC 0.3 VCC 0.2 VCC 0.4 VCC, p-to-p (minimum) |
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