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ST7LITE1XB 数据表(PDF) 115 Page - STMicroelectronics |
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ST7LITE1XB 数据表(HTML) 115 Page - STMicroelectronics |
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115 / 157 page  ST7LITE1xB 115/157 OPERATING CONDITIONS (Cont’d) The RC oscillator and PLL characteristics are temperature-dependent and are grouped in four tables. 13.3.5.1 Devices with ‘”6” or “3”order code suffix (tested for TA = -40 to +125°C) @ VDD = 5V Notes: 1. If the RC oscillator clock is selected, to improve clock stability and frequency accuracy, it is recommended to place a decoupling capacitor, typically 100nF, between the VDD and VSS pins as close as possible to the ST7 device. 2. See “INTERNAL RC OSCILLATOR ADJUSTMENT” on page 23 3. Data based on characterization results, not tested in production 4. Averaged over a 4ms period. After the LOCKED bit is set, a period of tSTAB is required to reach ACCPLL accuracy. 5. After the LOCKED bit is set ACCPLL is max. 10% until tSTAB has elapsed. See Figure 13 on page 24. 6. This period is the phase servo loop period. During this period, the frequency remains unchanged. 7. Guaranteed by design. Symbol Parameter Conditions Min Typ Max Unit fRC Internal RC oscillator fre- quency 1) RCCR = FF (reset value), TA=25°C,VDD=5V 700 kHz RCCR = RCCR02 ),TA=25°C,VDD=5V 992 1000 1008 ACCRC Accuracy of Internal RC oscillator with RCCR=RCCR02) TA=25°C,VDD=5V -0.8 +0.8 % TA=25°C, VDD=4.5 to 5.5V 3) -1 +1 % TA=25°C to +85°C,VDD=5V -3 +3 % TA=25°C to +85°C,VDD=4.5 to 5.5V 3) -3.5 +3.5 % TA=85°C to +125°C,VDD=5V -3.5 +5 % TA=85°C to +125°C,VDD=4.5 to 5.5V 3) -3.5 +6 % TA=-40 to +25°C, VDD=5V 3) -3 +7 % IDD(RC) RC oscillator current con- sumption TA=25°C,VDD=5V 6003) µA tsu(RC) RC oscillator setup time TA=25°C,VDD=5V 102) µs fPLL x8 PLL input clock 13) MHz tLOCK PLL Lock time5) 2ms tSTAB PLL Stabilization time5) 4ms ACCPLL x8 PLL Accuracy fRC = 1MHz@TA=25°C,VDD=4.5 to 5.5V 0.14) % fRC = 1MHz@TA=-40 to +85°C,VDD=5V 0.14) % tw(JIT) PLL jitter period 6) fRC = 1MHz 120 µs JITPLL PLL jitter ( ∆f CPU/fCPU)1 7) % IDD(PLL) PLL current consumption TA=25°C 6003) µA |
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