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ST7LITE1XB 数据表(PDF) 148 Page - STMicroelectronics |
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ST7LITE1XB 数据表(HTML) 148 Page - STMicroelectronics |
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148 / 157 page ![]() ST7LITE1xB 148/157 15 DEVICE CONFIGURATION AND ORDERING INFORMATION Each device is available for production in user pro- grammable versions (FLASH). ST7FLITE1xB devices are shipped to customers with a default program memory content (FFh). This implies that FLASH devices have to be con- figured by the customer using the Option Bytes. 15.1 OPTION BYTES The two option bytes allow the hardware configu- ration of the microcontroller to be selected. The option bytes can be accessed only in pro- gramming mode (for example using a standard ST7 programming tool). OPTION BYTE 0 OPT7 = Reserved, must always be 1. OPT6 = PKG Package selection 0: 16-pin package 1: 20-pin package OPT5:4 = CLKSEL Clock Source Selection When the internal RC oscillator is not selected (Option OSC=1), these option bits select the clock source: resonator oscillator or external clock Note: When the internal RC oscillator is selected, the CLKSEL option bits must be kept at their de- fault value in order to select the 256 clock cycle delay (see Section 7.5). OPT3:2 = SEC[1:0] Sector 0 size definition These option bits indicate the size of sector 0 ac- cording to the following table. OPT1 = FMP_R Read-out protection Readout protection, when selected provides a pro- tection against program memory content extrac- tion and against write access to Flash memory. Erasing the option bytes when the FMP_R option is selected will cause the whole memory to be erased first and the device can be reprogrammed. Refer to the ST7 Flash Programming Reference Manual and section 4.5 on page 14 for more de- tails 0: Read-out protection off 1: Read-out protection on OPT0 = FMP_W FLASH write protection This option indicates if the FLASH program mem- ory is write protected. Warning: When this option is selected, the pro- gram memory (and the option bit itself) can never be erased or programmed again. 0: Write protection off 1: Write protection on Clock Source Port C CLKSEL Resonator Ext. Osc Enabled/ Port C Disabled 00 Ext. Clock source: CLKIN on PB4 Ext. Osc Disabled/ Port C Enabled 01 on PC0 1 1 Reserved 1 0 Sector 0 Size SEC1 SEC0 0.5k 00 1k 01 2k 10 4k 11 OPTION BYTE 0 70 OPTION BYTE 1 70 Res. PKG CLKSEL SEC1 SEC0 FMP R FMP W PLL x4x8 PLL OFF PLL32 OFF OSC LVD1 LVD0 WDG SW WDG HALT Default Value 1111 0 1 0 0 1 1 1 0111 1 |
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