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RA4M2 数据表(PDF) 61 Page - Renesas Technology Corp |
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RA4M2 数据表(HTML) 61 Page - Renesas Technology Corp |
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61 / 93 page ![]() Note 1. For slave-mode transmission, SSIE has a path, through which the signal input from the SSILRCK0/SSIFS0 pin is used to generate transmit data, and the transmit data is logically output to the SSITXD0 pin. SSIBCK0 tHC tO, tI tLC tRC tFC Figure 2.44 SSIE clock input/output timing GTIOC2A, AUDIO_CLK (input) tEXH tEXL tEXr tEXcyc tEXf 1/2 VCC Figure 2.45 Clock input timing tSR tHR tDTR SSIBCK0 (Input or Output) SSILRCK0/SSIFS0 (input), SSIRXD0 (input) SSILRCK0/SSIFS0 (output), SSITXD0 (output) Figure 2.46 SSIE data transmit and receive timing when SSICR.BCKP = 0 RA4M2 Datasheet 2. Electrical Characteristics R01DS0367EJ0140 Rev.1.40 May 9, 2025 Page 61 of 93 |
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