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RA4M2 数据表(PDF) 89 Page - Renesas Technology Corp |
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RA4M2 数据表(HTML) 89 Page - Renesas Technology Corp |
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89 / 93 page  3.2 Access Cycles This section provides access cycle information for the I/O registers described in this manual. ● Registers are grouped by associated module. ● The number of access cycles indicates the number of cycles based on the specified reference clock. ● In the internal I/O area, reserved addresses that are not allocated to registers must not be accessed, otherwise operations cannot be guaranteed. ● The number of I/O access cycles depends on bus cycles of the internal peripheral bus, divided clock synchronization cycles, and wait cycles of each module. Divided clock synchronization cycles differ depending on the frequency ratio between ICLK and PCLK. ● When the frequency of ICLK is equal to that of PCLK, the number of divided clock synchronization cycles is always constant. ● When the frequency of ICLK is greater than that of PCLK, at least 1 PCLK cycle is added to the number of divided clock synchronization cycles. ● The number of write access cycles indicates the number of cycles obtained by non-bufferable write access. Note: This applies to the number of cycles when access from the CPU does not conflict with the instruction fetching to the external memory or bus access from other bus masters such as DTC or DMAC. Table A3.2 Access cycles (1 of 3) Peripherals Address Number of access cycles ICLK = PCLK ICLK > PCLK*1 Cycle Unit Related function From To Read Write Read Write RMPU, TZF, SRAM, BUS, DMACn, DMA, DTC, ICU 0x4000_0000 0x4000_6FFF 2 2 2 2 ICLK Renesas Memory Protection Unit, TrustZone Filter, SRAM Control, BUS Control, Direct memory access controller n, DMAC Module Activation, DTC Control Register, Interrupt Controller CPSCU, DBG, FCACHE 0x4000_8000 0x4001_CFFF 4 3 4 3 ICLK CPU System Security Control Unit, Debug Function, Flash Cache SYSC 0x4001_E000 0x4001_E3FF 5 4 5 4 ICLK System Control SYSC 0x4001_E400 0x4001_E5FF 9 8 5 to 8 5 to 8 PCLKB System Control PORTn, PFS 0x4008_0000 0x4008_0FFF 5 4 2 to 5 2 to 4 PCLKB Port n Control Registers, Pmn Pin Function Control Register ELC, RTC, IWDT, WDT, CAC 0x4008_2000 0x4008_3FFF 5 4 3 to 5 2 to 4 PCLKB Event Link Controller, Realtime Clock, Independent Watchdog Timer, Watchdog Timer, Clock Frequency Accuracy Measurement Circuit MSTP 0x4008_4000 0x4008_4FFF 5 4 2 to 5 2 to 4 PCLKB Module Stop Control POEG 0x4008_A000 0x4008_AFFF 5 4 3 to 5 2 to 4 PCLKB Port Output Enable Module for GPT USBFS 0x4009_0000 0x4009_03FF 6 5 3 to 6 3 to 5 PCLKB USB 2.0 FS Module USBFS 0x4009_0400 0x4009_04FF 4 3 1 to 4 1 to 3 PCLKB USB 2.0 FS Module RA4M2 Datasheet Appendix 3. I/O Registers R01DS0367EJ0140 Rev.1.40 May 9, 2025 Page 89 of 93 |
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