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RA4M2 数据表(PDF) 90 Page - Renesas Technology Corp |
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RA4M2 数据表(HTML) 90 Page - Renesas Technology Corp |
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90 / 93 page  Table A3.2 Access cycles (2 of 3) Peripherals Address Number of access cycles ICLK = PCLK ICLK > PCLK*1 Cycle Unit Related function From To Read Write Read Write SDHI0, SSIE0, IICn, IIC0WU 0x4009_2000 0x4009_FFFF 5 4 2 to 5 2 to 4 PCLKB SD Host Interface 0, Serial Sound Interface Enhanced, Inter-Integrated Circuit n, Inter-Integrated Circuit 0 Wake-up Unit CANn 0x400A_8000 0x400A_9FFF 5 4 2 to 5 2 to 4 PCLKB CANn Module CTSU 0x400D_0000 0x400D_FFFF 4 3 1 to 4 1 to 3 PCLKB Capacitive Touch Sensing Unit PSCU 0x400E_0000 0x400E_0FFF 5 4 2 to 5 2 to 4 PCLKB Peripheral Security Control Unit AGTn 0x400E_8000 0x400E_8FFF 7 4 5 to 7 2 to 4 PCLKB Low Power Asynchronous General purpose Timer n TSN 0x400F_3000 0x400F_3FFF 5 4 2 to 5 2 to 4 PCLKB Temperature Sensor CRC, DOC 0x4010_8000 0x4010_9FFF 5 4 2 to 5 2 to 4 PCLKA CRC Calculator, Data Operation Circuit SCIn 0x4011_8000 0x4011_8FFF 5*2 4*2 2 to 5*2 2 to 4*2 PCLKA Serial Communication Interface n SPIn 0x4011_A000 0x4011_AFFF 5*3 4*3 2 to 5*3 2 to 4*3 PCLKA Serial Peripheral Interface n SCE9 0x4016_1000 0x4016_1FFF 6 4 3 to 6 2 to 4 PCLKA Secure Cryptographic Engine GPT32n, GPT16n, GPT_OPS 0x4016_9000 0x4016_9FFF 7 4 4 to 7 2 to 4 PCLKA General PWM 32-Bit Timer n, General PWM 16-Bit Timer n, Output Phase Switching Controller ADC12n, DAC12 0x4017_0000 0x4017_2FFF 5 4 2 to 5 2 to 4 PCLKA 12bit A/D Converter n, 12-bit D/A converter QSPI 0x6400_0000 0x6400_000F 5 14 to *4 2 to 5 14 to *4 PCLKA Quad-SPI QSPI 0x6400_0010 0x6400_0013 25 to *4 6 to *4 25 to *4 5 to *4 PCLKA Quad-SPI QSPI 0x6400_0014 0x6400_0037 5 14 to *4 2 to 5 14 to *4 PCLKA Quad-SPI QSPI 0x6400_0804 0x6400_0807 4 3 1 to 4 1 to 3 PCLKA Quad-SPI Table A3.2 Access cycles (3 of 3) Peripherals Address Number of access cycles ICLK = FCLK ICLK > FCLK*1 Cycle Unit Related function From To Read Write Read Write FLAD, FACI 0x407F_C000 0x407F_EFFF 3 3 2 to 3 2 to 3 FCLK Data Flash, Flash Application Command Interface Note 1. If the number of PCLK or FCLK cycles is non-integer (for example 1.5), the minimum value is without the decimal point, and the maximum value is rounded up to the decimal point. For example, 1.5 to 2. 5 is 1 to 3. Note 2. When accessing a 16-bit register (FTDRHL, FRDRHL, FCR, FDR, LSR, and CDR), access is 2 cycles more than the value shown in Table A3.2. When accessing an 8-bit register (including FTDRH, FTDRL, FRDRH, and FRDRL), the access cycles are as shown in Table A3.2. Note 3. When accessing the 32-bit register (SPDR), access is 2 cycles more than the value in Table A3.2. When accessing an 8-bit or 16-bit register (SPDR_HA), the access cycles are as shown in Table A3.2. Note 4. The access cycles depend on the QSPI bus cycles. RA4M2 Datasheet Appendix 3. I/O Registers R01DS0367EJ0140 Rev.1.40 May 9, 2025 Page 90 of 93 |
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