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tSR

tHR

tDTR

SSIBCK0

(Input or Output)

SSILRCK0/SSIFS0 (input),

SSIRXD0 (input)

SSILRCK0/SSIFS0 (output),

SSITXD0 (output)

Figure 2.47

SSIE data transmit and receive timing when SSICR.BCKP = 1

tDTRW

SSILRCK0/SSIFS0 (input)

SSITXD0 (output)

MSB bit output delay after SSILRCK0/SSIFS0 change for slave

transmitter when DEL = 1, SDTA = 0 or DEL = 1, SDTA = 1, SWL[2:0] = DWL[2:0] in SSICR.

Figure 2.48

SSIE data output delay after SSILRCK0/SSIFS0 change

2.3.13

SD/MMC Host Interface Timing (m = 0 to 3)

Table 2.32

SD/MMC Host Interface signal timing

Conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register.

Clock duty ratio is 50%.

Parameter

Symbol

Min

Max

Unit

Test conditions

SD0CLK clock cycle

TSDCYC

—

Figure 2.49

SD0CLK clock high pulse width

TSDWH

6.5

—

SD0CLK clock low pulse width

TSDWL

6.5

—

SD0CLK clock rise time

TSDLH

—

SD0CLK clock fall time

TSDHL

—

SD0CMD/SD0DATm output data delay

TSDODLY

–7

SD0CMD/SD0DATm input data setup

TSDIS

4.5

—

SD0CMD/SD0DATm input data hold

TSDIH

1.5

—

RA4M2 Datasheet

2. Electrical Characteristics

R01DS0367EJ0140 Rev.1.40

May 9, 2025

Page 62 of 93

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