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AS7331

Functional Description

Datasheet

• PUBLIC

DS001047

• v4-00 • 2023-Mar-24

│ 39

Figure 33:

Achievable GAIN for Different Internal Clock Frequencies Chosen by CREG3:CCLK

CREG3:CCLK

[dec]

fCLK [MHz]

1.024

2.048

4.096

8.192

CREG1:GAIN [dec]

Adjustable GAIN

2048x

1024x

512x

256x

1024x

512x

256x

128x

64x

32x

16x

During the measurement cycle, within the conversion time TCONV, an input signal overdrive must be

avoided - even if it occurs limited in time, related to TCONV. In this case, the input light is too much

concerning the chosen irradiance responsivity Re, of the AS7331 tolerates. An internal function of the

analog conversion monitors all channels during the conversion process, in terms of the relation of

input light and chosen irradiance responsivity Re, determined via CREG1:GAIN. In case the input light

of at least one of the channels is too much, the status bit STATUS:ADCOF (see Figure 55) is set to

signal the problem and the chosen GAIN of the A/D converter (CREG1:GAIN) has to be decreased, to

reduce the irradiance responsivity Re, of the sensor.

7.5

Divider

To expand the measurement ranges, an internally implemented divider or pre-scaler can be used to

scale the results. This might be necessary if the resolution of the conversion is set to a value higher

than 16 bits. If the digital divider is used, the conversion result is downscaled according to the

equation:

Equation 5:

MRES

FSR

MRES

DIV

CLK

DIV











[dec]

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