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AS7331 数据表(PDF) 61 Page - ams-OSRAM AG |
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AS7331 数据表(HTML) 61 Page - ams-OSRAM AG |
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61 / 72 page ![]() Document Feedback AS7331 Register Description Datasheet • PUBLIC DS001047 • v4-00 • 2023-Mar-24 71 │ 60 Addr: 0h STATUS Bit Bit Name Default Access Bit Description 1 Measurement is in progress. 1 STANDBYSTATE - RO Value Standby 0 OFF 1 ON 0 POWERSTATE - RO Value Power Down state 0 OFF 1 ON (1) Overflow of the internal 24-bit conversion time counter – only possible in SYND mode with externally synchronized start and stop of conversion. (2) The status flag is generated while a measurement is in progress. It always matches to the actual results of the output register bank. (3) A reading process of the register STATUS always resets this status flag. (4) A reading process of the register STATUS and/or at least one result register always resets this status flag. The bit STATUS:OUTCONVOF, shows an overflow of the 24-bit counter of the internal reference for the conversion time. This can only occur i n SYND mode with CREG2:EN_TM = “1” and in case of accordingly long externally given conversion times. After a counter overflow, the counter starts again from zero. The bit STATUS:MRESOF, shows an overflow in one or more result registers of MRES1 … MRES3. This can only happen if the conversion time is longer than 216 (CREG1:TIME = 7…15 dec), in accordance with a higher input signal. The overflowed register stops at its maximum value, FFFFh. With the bit STATUS:ADCOF, an input signal overdrive is signalized, which could occur during the measurement cycle limited in time so that no overflow of the result registers (MRESOF) is necessarily produced. However, the measurement results are not correct in this case. To eliminate this issue, the irradiance responsivity (Re) of the sensor has to be decreased via CREG1:GAIN. The status bits OUTCONVOF, MRESOF, and ADCOF, always correspond to the actual content of the measurement result registers MRES1…3. The bits STATUS:LDATA and STATUS:NDATA, show the status of the measurement results. At the end of each measurement cycle, the results of the counters are stored in buffer registers. The flag NDATA is set to “1” to show the update (see Figure 56). With the start of each I²C read operation, the content of all buffer registers is transferred to the result registers. This ensures that during the I²C readout operation, the values of the result registers do not change. As long as an I²C-reading of the measurement result registers is in the process (no I²C stop condition has been sent), no further update of the measurement result registers concerning newer data of the buffer registers will happen. |
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