AS7331 datasheet(55/72 Pages) AMSOSRAM

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AS7331

Datasheet

• PUBLIC

DS001047

• v4-00 • 2023-Mar-24

│ 54

Addr: 7h

CREG2

Bit

Bit Name

Default

Access

Bit Description

Internal measurement of the

externally defined conversion

time via SYN pulse in SYND

mode is enabled (OUTCONV

results are generated as well as

temperature values for output

EN_DIV

Value

Function

Digital divider of the

measurement result registers is

disabled.

Digital divider of the

measurement result registers is

enabled (might be needed @

CREG1:TIME > 6 dec).

2:0

DIV

000

Value

Value of the divider (21+DIV[dec])

000

001

010

011

100

101

110

111

In SYND mode, the conversion time is externally controlled via pin SYN. In that case, the bit

CREG2:EN_TM enables the counting of internal clocks within the externally given conversion time, as

well as the access to the output register, OUTCONV, which contains the counting result. It is possible

to count several clocks up to 24 bits. In case this function is not used in SYND mode (equal to

CREG2:EN_TM =

“0”), no result for temperature measurement is generated and the values for the

output register TEMP will not be valid.

The bit CREG2:EN_DIV enables the internal prescaler, which could be interesting for conversion

times more than 16-

bits (CREG1:TIME ≥ 0111b) and if SYND mode is used. The value of CREG2:DIV

is only valid with CREG2:EN_DIV =

“1”. Then the measurement range is extended while the resolution

of the 16-bit register results is reduced at the same time (see chapter 7.5). Thus, it is also possible to

generate complete measurement results for conversion times from 217 to 224 system clocks

(CREG1:TIME). If the chosen value of the prescaler is too small, a counter overflow could occur,

which is shown by the bit STATUS:MRESOF of the result register bank.

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