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AS7331 数据表(PDF) 44 Page - ams-OSRAM AG

部件名 AS7331
功能描述  Spectral UVA/B/C Sensor
PDF  72 Pages
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制造商  AMSOSRAM [ams-OSRAM AG]
网页  https://ams-osram.com/
标志 AMSOSRAM - ams-OSRAM AG

AS7331 数据表(HTML) 44 Page - ams-OSRAM AG

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AS7331
Functional Description
Datasheet
• PUBLIC
DS001047
• v4-00 • 2023-Mar-24
71
│ 43
After the protocol starts, the data at the SDA pin must be fully stable during the high phase of the I²C
clock at the SCL pin. The change of the communication data at the SDA pin is only allowed during the
low phase of the SCL clock.
Figure 37:
Bit
– Transfer on I²C Bus
Each data transfer consists of 1 byte, which has to be followed by an acknowledge bit (A) (see
Figure 38). The bits arrive with the MSB first. The acknowledge signal shall be pulled low by the
receiver during the high period of the ninth clock pulse while the transmitter releases the SDA line.
When SDA stays high during the ninth clock pulse, the not acknowledge signal (NA) is output. After
the not acknowledge signal, the master generates either a stop or a repeated start condition,
depending on whether the master either wants to abort or start a new transfer. In the case of the
AS7331 as a slave, a not acknowledge (NA) is only generated if the device address did not match.
Figure 38:
I²C Write and Read Sequences
SCL
SDA
data line
stable;
data valid
change
of data
allowed
read sequence:
P: STOP cond.
S SLAVE ADDR. R/W A
0
REG ADDR. A
A: acknowledge
NA: not acknowledge
S: START cond.
Sr: repeated START cond.
DATA
A
DATA
NA P
. . .
Sr SLAVE ADDR.R/W
1
A
S: START cond.
P: STOP cond.
S SLAVE ADDR. R/W A
0
REG ADDR. A
DATA
A
DATA
A P
write sequence:
. . .
data transferred from slave to master
data transferred from master to slave
A: acknowledge
DATA
A
DATA
NA P
. . .
S SLAVE ADDR. R/W
1
A
short read sequence:
S: START cond.
P: STOP cond.
A: acknowledge
data transferred from slave to master
data transferred from master to slave
data transferred from slave to master
data transferred from master to slave



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