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db09284e_V3.01_preliminary_2017-07-06

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AS89020

V3.01

5 DESCRIPTION OF FUNCTION

5.1 Description

The AS89020 is a 4 channel, current input analog-to-digital converter (ADC). For each of 4 inputs the

AS89020 provides a transimpedance amplifier (TIA). The gain of transimpedance amplifier is separately

programmable for each channel. The transimpedance of the input amplifier for channels is selectable in 17

stages. In exactly the same way the FSR current (Full-Scale-Range current) of the ADC is adjusted. This

adjustment can be performed for every channel separately by programming the corresponding register

SW_RX. The AD conversion is started and controlled via the SPI and the channels are successive converted.

The channel order of the conversion process can be chosen and programmed via SPI using register

CH_ORDER. The AS89020 has implemented a temperature compensation of the transimpedance input

amplifier to achieve a high absolute accuracy and temperature stability of converted value.

The output signal of the transimpedance amplifier (VTX) is subsequently converted by an analog-to-digital

converter (ADC) to a 12 bit digital word. The input of the ADC is realized as a 4 channel track and hold

circuit, which can be switched into the track or hold mode by the signal CONVN or the signal CSN (part of

the SPI-interface). The track and hold circuit takes samples of each channel at the same time and holds

them internally stored in an analog memory.

The power supply for the device is typically 2.7 V to 3.6 V. The digital and the analog supplies are separated

to minimize the crosstalk of both parts inside the AS89020 circuitry.

5.2 Operational States

The AS89020 has 2 operational states – configuration and measurement. It is possible to toggle between

these two states by programming the bits 2 to 0 of register OSR. The configuration state is the default

state after the power-up phase including an internal power-on-reset. The configuration registers are set to

their default values after the power-on-reset. They can be changed via SPI command. All settings for the

measurement must be made in the configuration mode (e.g. setting FSR of ADC). During the configuration

mode the ADC is in reset state and the track and hold circuit is inactive.

The track and hold circuit and the ADC are active only in the measurement mode. Before the real ADC

conversion can be started, a tracking phase must occur (OSR: TRACK must be ,1b') with the minimum

length of tTRACK. With the falling edge of CSN or CONV (depending on the setting of CREG: STARTSIG) the

tracking phase is stopped and the 4 input signals for the ADC are sampled (hold phase of track and-hold

circuit) and the ADC conversion is started. The capture of input signals occurs simultaneously for all

channels. For one AD conversion (one channel), a 2-byte SPI communication is needed (equal to 16 SPI

clock cycles). The configuration registers are not readable and not writable while the AS89020 is in the

measurement state. The bit OSR:TRACK defines whether the next conversion or a new tracking follows

after the next falling edge of CSN.

5.3 Power Down Mode

The Power Down mode is selected by setting the PDN input level to ZERO or by programming a ,1b' into

the corresponding register OSR:PD or CH_PD. The register CH_PD affects only the transimpedance

amplifiers. The Power Down mode via PDN or register OSR:PD switches off the functionality of the full

analog part of the AS89020. The functionality of the digital Part and the SPI communication is not

interrupted during this mode. The device stays idle and the SPI-interface is enabled. The operational state,

which was used before the Power Down mode has been switched on, is preserved. Setting one or more

channels into Power Down via register CH_PD switches only the selected channels. If the Power Down mode

ends the AS89020 starts with all actual register settings. The device needs a start-up time of typically

200 ms. This time is at least necessary to load all external capacitors to their typical values for a proper

operation of the circuit (see also Table 3).