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db09284e_V3.01_preliminary_2017-07-06

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AS89020

V3.01

Figure 4: timing diagram of the analog-to-digital conversion

Figure 5: start of conversion with CONV or CSN

The accuracy of the AD conversion is determined by different effects. The duration of the tracking phase

(tTRACK) is very important for the accuracy of the current-to-digital conversion result and should not be

shorter than specified. To achieve the best possible accuracy, the SPI clock fSCLK should be not higher than

10MHz and the time tCSNS should be at least 2.5 µs. If the AS89020 is used with a power supply under

2.9 V, it is recommended that CREG: SETVB bit is set to ,1b’ to achieve the full accuracy of ADC.

TRACKING

HOLD / CONVERSION

SDO

b13

b14

b15

OSR=80h

b8

b1

b6

b7

b0

00h → continue with the

conversion of next channel

00h

→ continue with the conversion

80h

→ continue with new tracking

OSR = ,00

h’: continuation of the conversion of the next channel

OSR = ,80

h’: stop of the conversion and start of a new tracking

SDI

SCLK

CSN

TRACKING

HOLD / CONVERSION

CONVN

CSN

SCLK

SDO

BI T5

BI T6

BI T7

Start of Conversion with CONV (CREG:STARTSIG = ,1')

OSR=80h

INX

X

TRACKING

HOLD / CONVERSION

CONVN

CSN

SCLK

SDO

BI T5

BI T6

BI T7

Start of Conversion with CSN (CREG:STARTSIG = ,0')

OSR=80h

INX

X