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AS89020 数据表(PDF) 20 Page - ams-OSRAM AG |
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AS89020 数据表(HTML) 20 Page - ams-OSRAM AG |
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20 / 32 page ![]() ams.com db09284e_V3.01_preliminary_2017-07-06 Page 18 of 30 AS89020 V3.01 Table 7: Addressable Register Space ADDRESS [HEX] ACCESS7 NAME NO. OF SIGNIFICANT BITS DEFAULT [HEX] DESCRIPTION 00 wo OSR 8 02 operational state register 01 – – – – reserved 02 ro AGEN 8 40 API generation 03 – – – – reserved 04 – – – – reserved 05 – – – – reserved 06 rw CREG 8 A0 configuration register 07 rw SW_R0 6 01 transimpedance of channel 0 08 rw SW_R1 6 01 transimpedance of channel 1 09 rw SW_R2 6 01 transimpedance of channel 2 0A rw SW_R3 6 01 transimpedance of channel 3 0B rw CH_PD 4 0 channel Power Down 0C rw CH_ ORDER 8 1B channel order for the conversion 0D – – – – reserved 0E – – – – reserved 0F – – – – reserved 6.2 Operational State Register – OSR The write-only register OSR controls the device operational state (DOS), the general Power Down mode (PD) and the tracking behavior (TRACK) of the AS89020 according to Table 8. This register can be written at any time, independently of the actual operational state. Please note, reading this register always returns the value ,00h’ because the register is write-only. Table 8: Register OSR – Address 00h OPERATIONAL STATE REGISTER OSR NAME VALUE [B] AFFECTED OPERATIONAL STATE 08 sample input signal or start the AD conversion (active only in measurement state) 1 track input signal and stop AD conversion (active only in measurement state) 08 nominal operation, no Power Down mode 1 activate Power Down mode bit 5 to 3 - - reserved 7 ro – read-only, wo – write-only, rw – read-write, reading register with access write-only results in ,00h’ 8 Default after power-on-reset. |
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