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db09284e_V3.01_preliminary_2017-07-06

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AS89020

V3.01

5.4 AD Converter

The AS89020 utilizes the ADC for the on-chip analog-to-digital conversion of the input current. The full-

scale range current of the ADC is defined by 2 values. One important value is the current, which flows

through the pin REXT (direction out of the pin).The second part of the definition of full-scale range current

of ADC is the adjustment of the full-scale range using register SW_RX (see Table 3 and Table 11).

The digital data of the ADC output can be defined as

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I(INX):

input current at pin INX

IREFX:

equivalent reference current or equivalent FSR for channel X (see chapter 2.3 Table 3)

DOFFGEN: 0 if bit CREG:OFFGEN =,0b ’

63 if bit CREG:OFFGEN =,1b’ (see Table 10 and see chapter 6.4 )

OUTX:

digital result of the AD conversion for channel X (possible values: ,000h’ to ,FFFh’ )

The accuracy of the reference current source at pin REXT has a direct influence on the overall ADC

characteristic. This pin has to be connected as suggested by Figure 3. An internal voltage is generated at

pin REXT (typically 1.2 V). The resulting reference current is equal to V(REXT) / 200 kΩ, which is 6 µA. The

overall ADC accuracy is directly influenced by the performance of the external resistor (temperature

coefficient and absolute value and its tolerance).

Figure 3: External Wiring of Pin REXT

5.5 AD Conversion

The AD conversion is only possible in measurement mode (OSR register bit 2 to bit 0 setting to ,011b’).

The operation of conversion is controlled by the signals CSN or CONV (depending on setting of

CREG:STARTSIG), SCLK and the settings in register OSR. The conversion process consist of 2 parts. At first

the output voltages of input amplifiers are simultaneously sampled. Afterwards the sampled values are

converted one after another with the successive approximation (SAR-) ADC.

Every conversion process starts with a tracking phase at a duration of minimal tTRACK (bit OSR:TRACK

=,1b’). The falling edge of CSN or CONV takes a sample of each channel. The sampling occurs only if the

bit OSR:TRACK is set to ,1b.’

The signal SCLK controls the actual analog-to-digital conversion. SCLK is not only the SPI clock during the

conversion, but also the clock signal for the ADC. Parallel to the conversion the transfer of output data

takes place via SPI interface. 16 clock cycles are needed for the conversion of one channel (one sample)

and the transfer of the result. The format of result output is described in Table 14. The further behavior of

the IC is defined by sending 2 byte over SDI for programming the OSR register during the conversion. The

setting ,00h’ of the OSR defines that the conversion of the next channel follows (corresponding to the order

in register CH_ORDER). A setting of ,80h’ starts a new tracking phase after the actual conversion ended.

Figure 4 shows the timing diagram of the conversion cycle in the measurement state. Figure 5 shows the

different sample points for CONVN and CSN. If bit CREG:STARTSIG=,1b’ the signal CONVN can be used to

synchronize the input sampling time point at an external event. If bit CREG:STARTSIG=,0b’ the signal CSN

acts as part of a software command for the start of the conversion while CONVN must stay high in that

case.

V(REXT) / 200 kΩ

200 kΩ