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RZ/T2ME 数据表(PDF) 97 Page - Renesas Technology Corp |
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RZ/T2ME 数据表(HTML) 97 Page - Renesas Technology Corp |
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97 / 116 page  Table 2.37 ΔΣ interface timing Parameter Symbol Min. Max. Unit Reference figure DSMIF Clock cycle Master tDScyc 40 200 ns Figure 2.78 Slave 40 200 Clock high level Master tDSCKWH 16 — ns Slave 16 — Clock low level Master tDSCKWL 16 — ns Slave 16 — Setup time Master tSU 15 — ns Figure 2.79, Figure 2.80 Slave 5 — Hold time Master tH 0 — ns Slave 5 — MCLKn (n = 0 to 5) tDScyc tDSCKWH tDSCKWL Figure 2.78 Clock input/output timing MCLKn (input or output) tSU n = 0 to 5 MDATn (input) tH Figure 2.79 Reception timing (MCLKn rising synchronous) MCLKn (input or output) tSU MDATn (input) tH Figure 2.80 Reception timing (MCLKn falling synchronous) 2.5.5.14 Ethernet Interface Timing Conditions: VOH = VCC18 × 0.5, VOL = VCC18 × 0.5, C = 15 pF (RGMII)*1 RZ/T2ME Datasheet 2. Electrical Characteristics R01DS0441EJ0110 Rev.1.10 Mar 13, 2026 Page 97 of 116 |
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