ST7LITE3XF2 datasheet(143/173 Pages) STMICROELECTRONICS

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ST7LITE3xF2

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13.5 CLOCK AND TIMING CHARACTERISTICS

Subject to general operating conditions for VDD, fOSC, and TA.

13.5.1 General Timings

13.5.2 External Clock Source

Notes:

1. Guaranteed by Design. Not tested in production.

2. Data based on typical application software.

3. Time measured between interrupt event and interrupt vector fetch.

∆t

c(INST) is the number of tCPU cycles needed to fin-

ish the current instruction execution.

4. Data based on design simulation and/or technology characteristics, not tested in production.

Figure 83. Typical Application with an External Clock Source

Symbol

Parameter 1)

Conditions

Min

Typ 2)

Max

Unit

tc(INST)

Instruction cycle time

fCPU=8MHz

tCPU

250

375

1500

tv(IT)

Interrupt reaction time 3)

tv(IT) = ∆tc(INST) + 10

fCPU=8MHz

tCPU

1.25

2.75

µs

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VOSC1H or VCLKIN_H

OSC1/CLKIN input pin high level voltage

see Figure 83

0.7xVDD

VDD

VOSC1L or VCLKIN_L

OSC1/CLKIN input pin low level voltage

VSS

0.3xVDD

tw(OSC1H) or tw(CLKINH)

tw(OSC1L) or tw(CLKINL)

OSC1/CLKIN high or low time 4)

tr(OSC1) or tr(CLKIN)

tf(OSC1) or tf(CLKIN)

OSC1/CLKIN rise or fall time 4)

OSCx/CLKIN Input leakage current

VSS≤VIN≤VDD

±1

µA

OSC1/CLKIN

OSC2

fOSC

EXTERNAL

ST72XXX

CLOCK SOURCE

Not connected internally

VOSC1L or VCLKINL

VOSC1H or VCLKINH

tr(OSC1 or CLKIN) tf(OSC1 or CLKIN)

tw(OSC1H or CLKINH)

tw(OSC1L or CLKINL)

90%

10%

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