ST10 datasheet(62/65 Pages) STMICROELECTRONICS

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ST10C167

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The formula for SSC Clock Cycle time is : t300 = 4 TCL * (<SSCBR> + 1)

Where <SSCBR> represents the content of the SSC Baud rate register, taken as unsigned 16-bit integer.

Notes 1. The phase and polarity of shift and latch edge of SCLK is programmable. This figure uses the leading clock edge as shift edge (drawn

in bold), with latch on trailing edge (SSCPH = 0b), Idle clock line is low, leading clock edge is low-to-high transition (SSCPO = 0b).

2. The bit timing is repeated for all bits to be transmitted or received.

Slave mode

VCC =5V ±10%, VSS = 0V, CPU clock = 25MHz, TA = -40 to +125°C, CL = 100pF

Note

1. Timing guaranteed by design.

Figure 25 : SSC master timing

Symbol

Parameter

Max Baud rate=6.25MBd

(<SSCBR> = 0001h)

Variable Baud rate

(<SSCBR>=0001h-FFFFh )

Unit

Min.

Max.

Min.

Max.

t310

SSC clock cycle time

160

8 TCL

262144 TCL

t311

SSC clock high time

–

t310/2 - 10

–ns

t312

SSC clock low time

–

t310/2 - 10

–ns

t313

SSC clock rise time

–

t314

SSC clock fall time

–

t315

Write data valid after shift edge

–

2 TCL + 14

t316

Write data hold after shift edge

–

t317p SR Read data setup time before latch edge,

phase error detection on (SSCPEN = 1)

100

–

4TCL + 20

–

t318p SR Read data hold time after latch edge,

phase error detection on (SSCPEN = 1)

140

–

6TCL + 20

–

t317

Read data setup time before latch edge,

phase error detection off (SSCPEN = 0)

–

t318

Read data hold time after latch edge,

phase error detection off (SSCPEN = 0)

0–

–

t303

t304

305

306

1st Out Bit

Last Out Bit

2nd Out Bit

300

302

301

t307

2nd.In Bit

1st.In Bit

t308

307

Last.In Bit

308

SCLK

MTSR

MRST

XX - ELECTRICAL CHARACTERISTICS (continued)

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