ST10 datasheet(19/65 Pages) STMICROELECTRONICS

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ST10C167

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IX.2 - GPT2

The GPT2 module provides precise event control

and time measurement. It includes two timers (T5,

T6) and a capture/reload register (CAPREL). Both

timers can be clocked with an input clock which is

derived from the CPU clock via a programmable

prescaler or with external signals. The count

direction (up/down) for each timer is programma-

ble by software or may additionally be altered

dynamically by an external signal on a port pin

(TxEUD). Concatenation of the timers is sup-

ported via the output toggle latch (T6OTL) of timer

T6 which changes its state on each timer over-

flow/underflow.

The state of this latch may be used to clock timer

T5, or it may be output on a port pin (T6OUT). The

overflows/underflows of timer T6 can additionally

be used to clock the CAPCOM timers T0 or T1,

and to cause a reload from the CAPREL register.

The CAPREL register may capture the contents of

timer T5 based on an external signal transition on

the corresponding port pin (CAPIN), and timer T5

may optionally be cleared after the capture proce-

dure. This allows absolute time differences to be

measured or pulse multiplication to be performed

without software overhead.

The capture trigger (timer T5 to CAPREL) may

also be generated upon transitions of GPT1 timer

T3 inputs T3IN and/or T3EUD. This is advanta-

geous when T3 operates in Incremental Interface

Mode.

Table 7 lists the timer input frequencies, resolution

and periods for each pre-scaler option at 25MHz

CPU clock.

This also applies to the Gated Timer Mode of T6

and to the auxiliary timer T5 in Timer and Gated

Timer Mode.

Figure 5 : Block diagram of GPT1

2n n=3...10

T2EUD

T2IN

CPU Clock

T3EUD

T4IN

T3IN

T4EUD

Mode

Control

Mode

Control

Mode

Control

GPT1 Timer T2

GPT1 Timer T3

GPT1 Timer T4

T3OTL

Reload

Capture

U/D

Reload

Capture

Interrupt

Request

Interrupt

Request

Interrupt

Request

T3OUT

U/D

IX - GENERAL PURPOSE TIMER UNIT (continued)

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