ST10 datasheet(58/65 Pages) STMICROELECTRONICS

58 / 65 page

ST10C167

58/65

XX - ELECTRICAL CHARACTERISTICS (continued)

XX.4.11 - CLKOUT and READY

VDD =5V ± 10%, VSS = 0V, TA = -40 to +125°C

CL (for Port0, Port1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100pF

CL (for Port 6, CS) = 100pF

Notes 1.These timings are given for test purposes only, in order to assure recognition at a specific clock edge.

2. Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This adds even more time

for deactivating READY.

The 2tA and tC refer to the next following bus cycle, tF refers to the current bus cycle.

Table 20 : CLKOUT and READY characteristics

Symbol

Parameter

Max. CPU Clock

= 25MHz

Variable CPU Clock

1/2TCL = 1 to 25MHz

Unit

Min.

Max.

Min.

Max.

t29

CLKOUT cycle time

2TCL

t30

CLKOUT high time

–

TCL – 6

–

t31

CLKOUT low time

–

TCL – 10

–

t32

CLKOUT rise time

–

t33

CLKOUT fall time

–

t34

CLKOUT rising edge to ALE falling edge

0 + tA

10 + tA

0+ tA

10 + tA

t35

Synchronous READY setup time

to CLKOUT

–

t36

Synchronous READY hold time

after CLKOUT

4–

–

t37

Asynchronous READY low time

–

2TCL + 14

–

t58

Asynchronous READY setup time 1

–

t59

Asynchronous READY hold time 1

4–

–

t60

Async. READY hold time after RD, WR high

(Demultiplexed Bus) 2

00 + 2tA

+tC +tF

TCL - 20

+2tA +tC +tF

ST10 数据表(PDF) 58 Page - STMicroelectronics

ST10 数据表(HTML) 58 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65

数据表下载