ST10 datasheet(52/65 Pages) STMICROELECTRONICS

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ST10C167

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XX.4.10 - Demultiplexed bus

VDD =5V ± 10%, VSS = 0V, TA = -40 to +125°C

CL (for Port0, Port1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100pF,

CL (for Port 6, CS) = 100pF

ALE cycle time = 4 TCL + 2tA +tC +tF (80ns at 25MHz CPU clock without wait states)

Table 19 : Demultiplexed bus characteristics

Symbol

Parameter

Max. CPU Clock

= 25MHz

Variable CPU Clock

1/2TCL = 1 to 25MHz

Unit

Min.

Max.

Min.

Max.

ALE high time

10 + tA

–

TCL - 10+ tA

–ns

Address setup to ALE

4 + tA

–

TCL - 16+ tA

–ns

ALE falling edge to RD, WR (with

RW-delay)

10 + tA

–

TCL - 10 + tA

–ns

ALE falling edge to RD, WR (no

RW-delay)

-10 + tA

–

-10 + tA

–ns

t12

RD, WR low time (with RW-delay)

30 + tC

–

2TCL - 10 + tC

–ns

t13

RD, WR low time (no RW-delay)

50 + tC

–

3TCL - 10 + tC

–ns

t14

RD to valid data in (with RW-delay)

–

20 + tC

–2TCL - 20 + tC

t15

RD to valid data in (no RW-delay)

–

40 + tC

–3TCL - 20 + tC

t16

ALE low to valid data in

–

40 + tA +tC

–

3TCL - 20

+tA +tC

t17

Address/Unlatched CS to valid data

–50 + 2tA +tC

–

4TCL - 30

+2tA +tC

t18

Data hold after RD rising edge

–

t20

Data float after RD rising edge

(with RW-delay1)

–26 + tF

–

2TCL - 14

+tF +2tA

t21

Data float after RD rising edge

(no RW-delay1)

–10 + tF

–TCL - 10

+tF +2tA

t22

Data valid to WR

20 + tC

–

2TCL- 20 + tC

–ns

t24

Data hold after WR

10 + tF

–

TCL - 10+ tF

–ns

t26

ALE rising edge after RD, WR

-10 + tF

–

-10 + tF

–ns

t28

Address/Unlatched CS hold after

RD, WR 2

0+ tF

–0 + tF

–ns

t38

ALE falling edge to Latched CS

-4 - tA

10 - tA

-4 - tA

10 - tA

t39

Latched CS low to Valid Data In

–

40 + tC+2tA

–

3TCL - 20

+tC +2tA

t41

Latched CS hold after RD, WR

6 + tF

–

TCL - 14 + tF

–ns

t42

ALE falling edge to RdCS, WrCS

(with RW-delay)

16 + tA

–

TCL - 4 + tA

–ns

XX - ELECTRICAL CHARACTERISTICS (continued)

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