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ST10 数据表(PDF) 42 Page - STMicroelectronics |
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ST10 数据表(HTML) 42 Page - STMicroelectronics |
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42 / 65 page ![]() ST10C167 42/65 XX.4.1 - Definition of internal timing The internal operation of the ST10C167 is controlled by the internal CPU clock fCPU. Both edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles) operations. The specification of the external timing (AC Characteristics) therefore depends on the time between two consecutive edges of the CPU clock, called “TCL” periods (see Figure 11). The CPU clock signal can be generated by different mechanisms. The duration of TCL periods and their variation (and also the derived external timing) depends on the mechanism used to generate fCPU. This influence must be regarded when calculating the timings for the ST10C167. The example for PLL operation shown in Figure 11 refers to a PLL factor of 4. The mechanism used to generate the CPU clock is selected during reset by the logic levels on pins P0.15-13 (P0H.7-5). XX.4.2 - Clock generation modes Table 18 shows the association of the combinations of these three bits with the respective clock generation mode. Notes 1. The external clock input range refers to a CPU clock range of 10...25MHz. 2. The maximum frequency depends on the duty cycle of the external clock signal. Figure 11 : Generation mechanisms for the CPU clock Table 17 : CPU Frequency Generation P0.15-13 (P0H.7-5) CPU Frequency fCPU =fXTAL xF External Clock Input Range 1 Notes 111 FXTAL x 4 2.5 to 6.25MHz Default configuration 110 FXTAL x 3 3.33 to 8.33MHz 101 F XTAL x 2 5 to 12.5MHz 100 FXTAL x 5 2 to 5MHz 011 FXTAL x 1 1 to 25MHz Direct drive 2 010 FXTAL x 1.5 6.66 to 16.6MHz 001 FXTAL / 2 2 to 50MHz CPU clock via prescaler 000 FXTAL x 2.5 4 to 10MHz TCL TCL TCL TCL fCPU fXTAL fCPU fXTAL Phase locked loop operation Direct Clock Drive TCL TCL fCPU fXTAL Prescaler Operation XX - ELECTRICAL CHARACTERISTICS (continued) |
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