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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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ST10 数据表(PDF) 63 Page - STMicroelectronics |
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ST10 数据表(HTML) 63 Page - STMicroelectronics |
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63 / 65 page  ST10C167 63/65 The formula for SSC Clock Cycle time is: t310 = 4 TCL * (<SSCBR> + 1) Where <SSCBR> represents the content of the SSC Baud rate register, taken as unsigned 16-bit integer. Notes 1. The phase and polarity of shift and latch edge of SCLK is programmable. This figure uses the leading clock edge as shift edge (drawn in bold), with latch on trailing edge (SSCPH = 0b), Idle clock line is low, leading clock edge is low-to-high transition (SSCPO = 0b). 2. The bit timing is repeated for all bits to be transmitted or received. Figure 26 : SSC slave timing t 313 t 314 t 315 t 315 t 315 t 316 1st Out Bit Last Out Bit 2nd Out Bit t 310 t 312 t 311 1) 2) t 317 2nd.In Bit 1st.In Bit t 318 t 317 Last.In Bit t 318 SCLK MRST MTSR XX - ELECTRICAL CHARACTERISTICS (continued) |
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