ST10 datasheet(46/65 Pages) STMICROELECTRONICS

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ST10C167

46/65

t10

Address float after RD, WR

(with RW-delay)

–6

–

t11

Address float after RD, WR (no

RW-delay)

–

TCL + 6

t12

RD, WR low time (with RW-delay)

30 + tC

–

2TCL - 10 + tC

–ns

t13

RD, WR low time (no RW-delay)

50 + tC

–

3TCL - 10 + tC

–ns

t14

RD to valid data in (with

RW-delay)

–20 + tC

–

2TCL - 20+ tC

t15

RD to valid data in (no RW-delay)

–

40 + tC

–

3TCL - 20+ tC

t16

ALE low to valid data in

–

40 + tA +tC

–

3TCL - 20

+tA +tC

t17

Address/Unlatched

to valid

data in

–50 + 2tA +tC

–

4TCL - 30

+2tA +tC

t18

Data hold after RD rising edge

–

t19

Data float after RD

–

26 + tF

–

2TCL - 14 + tF

t22

Data valid to WR

20 + tC

–

2TCL - 20 + tC

–ns

t23

Data hold after WR

26 + tF

–2TCL - 14 + tF

–ns

t25

ALE rising edge after RD, WR

26 + tF

–2TCL - 14 + tF

–ns

t27

Address/Unlatched CS hold after

RD, WR

26 + tF

–2TCL - 14 + tF

–ns

t38

ALE falling edge to Latched CS

-4 - tA

10 - tA

-4 - tA

10 - tA

t39

Latched CS low to valid data in

–

40 + tC +2tA

–

3TCL - 20

+tC +2tA

t40

Latched CS hold after RD, WR

46 + tF

–3TCL - 14 + tF

–ns

t42

ALE fall. edge to RdCS, WrCS

(with RW delay)

16 + tA

–

TCL - 4 + tA

–ns

t43

ALE fall. edge to RdCS, WrCS

(no RW delay)

-4 + tA

–-4 + tA

–ns

t44

Address float after RdCS, WrCS

(with RW delay)

–0

–

t45

Address float after RdCS, WrCS

(no RW delay)

–

TCL

t46

RdCS to Valid Data In (with RW

delay)

–16 + tC

–

2TCL - 24 + tC

t47

RdCS to Valid Data In (no RW

delay)

–36 + tC

–

3TCL - 24 + tC

Table 18 : Multiplexed bus characteristics (continued)

Symbol

Parameter

Max. CPU Clock

= 25MHz

Variable CPU Clock

1/2TCL = 1 to 25MHz

Unit

Min.

Max.

Min.

Max.

XX - ELECTRICAL CHARACTERISTICS (continued)

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