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ST62T35B 数据表(PDF) 28 Page - STMicroelectronics

部件名 ST62T35B
功能描述  8-BIT OTP/EPROM MCUs WITH A/D CONVERTER, 16-BIT AUTO-RELOAD TIMER, EEPROM, SPI AND UART
PDF  82 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST62T35B 数据表(HTML) 28 Page - STMicroelectronics

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ST62T35B/E35B
IINTERRUPTS (Cont’d)
Interrupt Polarity Register (IPR)
Address: DAh
—
Read/Write
In conjunction with IOR register ESB bit, the polar-
ity of I/O pins triggered interrupts can be selected
by setting accordingly the Interrupt Polarity Regis-
ter (IPR). If a bit in IPR is set to one the corre-
sponding port interrupt is inverted (e.g. IPR bit 2 =
1 ; port C generates interrupt on rising edge. At re-
set, IPR is cleared and all port interrupts are not
inverted (e.g. Port C generates interrupts on fall-
ing edges).
Bit 7 - Bits 5 =
Unused.
Bit 4 =
Port E Interrupt Polarity.
Bit 3 =
Port D Interrupt Polarity.
Bit 2 =
Port C Interrupt Polarity.
Bit 1=
Port A Interrupt Polarity.
Bit 0 =
Port B Interrupt Polarity.
Tables 11. I/O Interrupts selections according to IPR, IOR programming
70
-
-
-
PortE PortD PortC PortA PortB
GEN
IPR3
IPR0
IOR5
Port B occurence
Port D occurence
Interrupt
source
1
0
0
0
falling edge
falling edge
2
1
0
0
1
rising edge
rising edge
1
0
1
0
rising edge
falling edge
1
0
1
1
falling edge
rising edge
1
1
0
0
falling edge
rising edge
1
1
0
1
rising edge
falling edge
1
1
1
0
rising edge
rising edge
1
1
1
1
falling edge
falling edge
0
X
X
X
Disabled
Disabled
GEN
IPR4
IPR1
IOR6
Port A occurence
Port E occurence
Interrupt
source
1
0
0
0
falling edge
falling edge
1
1
0
0
1
low level
low level
1
0
1
0
rising edge
falling edge
1
0
1
1
high level
low level
1
1
0
0
falling edge
rising edge
1
1
0
1
low level
high level
1
1
1
0
rising edge
rising edge
1
1
1
1
high level
high level
0
X
X
X
Disabled
Disabled
IPR2
Port C occurence
Interrupt source
0
falling edge
0
1
rising edge
27



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