ST62T35B datasheet(48/82 Pages) STMICROELECTRONICS

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ST62T35B/E35B

TIMINGS MEASUREMENT MODES(Cont’d)

4.3.3.2 Timing measurement without startup

control

The down counter is in free running mode with

RUNRES bit set and RELOAD bit cleared. This

means counter automatically restarts from FFFFh

on zero overflow and signal generation on PWM

and OVF pins is not affected.

Two independent capture paths exist to CP and

RLCP, which are both Read only registers. CP1 is

the source (Configurable polarity) for a capture

into RLCP while CP2 is the source (Configurable

polarity) of a capture into CP.

Independently of CP2 signal, if CP1FLG and

CP1ERR are cleared, the first active edge on CP1

will trigger a capture into RLCP, triggering

CP1FLG. As long as CP1FLG has not been

cleared, a second following active edge will trig

CP1ERR without any capture into neither RLCP

nor CP.

Independently of CP1 signal, if CP2FLG and

CP2ERR are cleared, the first active edge on CP2

will trigger a capture into CP, triggering CP2FLG.

As long as CP2FLG has not been cleared, a sec-

ond following active edge will trig CP2ERR without

any capture into neither RLCP or CP.

4.3.4 INTERRUPT CAPABILITIES

The interrupt source latches of the ARTIMER16

are always enabled and set any time the interrupt

condition occurs.

The interrupt output is a logical OR of five logical

ANDs:

– INT = [(CP1FLG & CP1IEN)

– OR (CP2FLG & CP2IEN)

– OR(OVFFLG & OVFIEN)

– OR(COMPFLG & CMPIEN)

– OR (ZEROFLG & ZEROIEN)]

Thus, if any enable bit is 1, the interrupt output of

the ARTIMER16 goes high when the respective

flag is set. If no enable bit is 1, and one of the in-

terrupt flags is set, the interrupt output remains 0,

but if the respective enable bit is set to 1 through a

write operation, the interrupt output will go high,

signalling the interrupt to the Core.

Figure 29. . Positive CP1 - to negative CP2-Edge Measurement (CP1POL = 1, CP2POL = 0)

Application Note:

Depending on polarity setting for CP1/CP2, and of

CP1/CP2 connections, phase, period and pulse

width measurements can be achieved. The total

independence between CP1 and CP2 captures al-

lows phase detection by measuring which of

CP1FLG or CP2FLG is set at first following a reset

of these flags.

VR02006F

COUNTER

CP1

CP2

Capture into RLCP

Set CP1FLG

Set CP1ERR

Set CP2FLG

Capture into CP

Set CP2ERR

CP1=CP2

CP1POL=CP2POL

Measurement

Yes

Period

Yes

Pulse width

Phase

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