ST62T35B datasheet(44/82 Pages) STMICROELECTRONICS

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ST62T35B/E35B

CENTRAL COUNTER (Cont’d)

4.3.1.3 Capture functions

Content of the counter CT can always be down-

loaded (captured) into the CP register at selecta-

ble event occurrence on pins CP1 and CP2, while

capture in RLCP is possible only when the bit

RELOAD is cleared.

Capture functions with RELOAD cleared are used

for period or pulse width measurements with input

CP2, or for phase measurements between two

signals on CP1 and CP2, with the counter in free

running mode. In these modes, counter values by

the two events occurence are stored into RLCP

and CP and the counter remains in free running

mode.

Capture functions with RELOAD set, are used for

same application purpose, but in that case, the

first event reloads the counter from RLCP while

the second event captures the counter content

into the CP register. Therefore, the counter is not

in free running mode for other functions since the

down counting start is initiated by either CP1, CP2

or RUNRES event according to RLDSEL1 and

RLDSEL2 bit.

4.3.2 SIGNAL GENERATION MODES

4.3.2.1 Output modes

Any

positive

comparison

0000h

MASK&CMP, and any overflow occurence can be

used to control the OVF or PWM output pins in

various modes defined by bits OVFMD, PWM-

POL, PWMEN and PWMMD.

PWM pin output modes

OVF pin output modes

* The OVF pin is reset by clearing the flag OVF-

FLG.

4.3.2.2 Frequency and duty cycles on PWM

pins

In Set/Reset mode (PWMMD=0), the period on

the PWM pin is the time between two matched

masked comparison to 0000h, at which PWM pin

is set (PWMPOL=1) or reset (PWMPOL=0). As

long as no reload function from RLCP is per-

formed (RELOAD bit cleared) and no mask is

used, this value is 2

16 x Psc x Tclk. If, on the con-

trary, reload function or a mask are used, the fre-

quency is controlled through the RLCP and MASK

values (Figure 25.). The condition to reset (PWM-

POL=1) or set back (PWMPOL=0) PWM pin is a

matched masked comparison to CMP. Given a

RLCP and MASK values within the Table 1, CMP

defines the duty cycle.

In Toggle mode (PWMMD=1), PWM pin changes

of state at each positive masked comparison to

CMP value. The frequency is half the frequency in

Set/Reset mode and the duty-cycle is always

50%.

4.3.2.3 Frequency and duty cycles on OVF pin

OVF pin activation is directed by the timer over-

flow occurence and therefore its frequency de-

pends only of the downcounting time from the re-

load value to 0000h. This means its period is

equal to T= (RLCP+1) x Psc x Tclk in Set/Reset

mode and 2 x (RLCP+1) x Psc x Tclk in Toggle

mode.

Duty cycle is controlled in Set/Reset mode

(OVFMD cleared) by software, since OVF pin can

be reset only by clearing the OVFFLG bit. In tog-

gle mode (OVFMD set), the duty cycle is always

50%.

Achievable periods on PWM pin

Note: n is the position of the most significant bit of MASK value.

MASK & CNT

= 0000h

yes

MASK&CT=

MASK&CMP

yes

PWMEN

PWMMD

PWMPOL

PWM pin

Reset Set

Set Reset Toggle

Zero overflow (OVFFLG)

OVFMD

OVF pin

Set*

Toggle

Mask value

FFFFh

xxxxh

Period in Set/Reset mode (PWMMD=0)

(RLCP+1) x Psc x Tclk

(n+1) x Psc x Tclk

Period in Toggle mode (PWMMD=1)

2 x (RLCP+1) x Psc x Tclk

2 x 2

(n+1) x Psc x Tclk

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