ST62T35B datasheet(60/82 Pages) STMICROELECTRONICS

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ST62T35B/E35B

SERIAL PERIPHERAL INTERFACE(Cont’d)

After 8 clock pulses (D7..D0) the output Q4 of the

4-bit binary counter becomes low, disabling the

clock from the counter and the data/shift register.

Q4 enables the clock to generate an interrupt on

the 8th clock falling edge as long as no reset of the

counter (processor write into the 8-bit data/shift

interrupt is disabled. The interrupt is active when

writing data in the shift register and desactivated

when writing any data in the SPI Interrupt Disable

The generation of an interrupt to the Core pro-

vides information that new data is available (input

mode) or that transmission is completed (output

mode), allowing the Core to generate an acknowl-

edge on the 9th clock pulse (I C-bus).

The interrupt is initiated by a high to low transition,

and therefore interrupt options must be set ac-

cordingly as defined in the interrupt section.

After power on reset, or after writing the data/shift

is enabled. In this condition the data shift register

is ready for reception. No start condition has to be

detected. Through the user software the Core may

pull down the Sin line (Acknowledge) and slow

down the SCL, as long as it is needed to carry out

data from the shift register.

I C-bus Master-Slave, Receiver-Transmitter

When pins Sin and Sout are externally connected

together it is possible to use the SPI as a receiver

as well as a transmitter. Through software routine

(by using bit-set and bit-reset on I/O line) a clock

can be generated allowing I C-bus to work in mas-

ter mode.

When implementing an I C-bus protocol, the start

condition can be detected by setting the processor

into a wait for start condition by enabling the inter-

rupt of the I/O port used for the Sin line. This frees

the processor from polling the Sin and SCL lines.

After the transmission/reception the processor

has to poll for the STOP condition.

In slave mode the user software can slow down

the SCL clock frequency by simply putting the

SCL I/O line in output open-drain mode and writ-

ing a zero into the corresponding data register bit.

As it is possible to directly read the Sin pin directly

through the port register, the software can detect a

difference between internal data and external data

(master mode). Similar condition can be applied to

the clock.

Three (Four) Wire Serial Bus

It is possible to use a single general purpose I/O

pin (with the corresponding interrupt enabled) as a

chip enable pin. SCL acts as active or passive

clock pin, Sin as data in and Sout as data out (four

wire bus). Sin and Sout can be connected togeth-

er externally to implement three wire bus.

Note:

When the SPI is not used, the three I/O lines (Sin,

SCL, Sout) can be used as normal I/O, with the

following limitation: bit Sout cannot be used in

open drain mode as this enables the shift register

output to the port.

It is recommended, in order to avoid spurious in-

terrupts from the SPI, to disable the SPI interrupt

(the default state after reset) i.e. no write must be

made to the 8-bit shift register. An explicit interrupt

disable may be made in software by a dummy

write to the SPI interrupt disable register.

SPI Data/Shift Register

Address: DDh - Read/Write (SDSR)

A write into this register enables SPI Interrupt after

8 clock pulses.

SPI Interrupt Disable Register

Address: DCh - Read/Write (SIDR)

A dummy write to this register disables SPI Inter-

rupt.

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