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ST62T35B 数据表(PDF) 36 Page - STMicroelectronics |
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ST62T35B 数据表(HTML) 36 Page - STMicroelectronics |
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36 / 82 page ![]() 36/82 ST62T35B/E35B I/O PORTS (Cont’d) 4.1.3 ARTimer alternate functions As long as PWMEN (resp. OVFEN) bit is kept low, the PA3/PWM (resp. PA2/OVF) pin is used as standard I/O pin and therefore can be configured in any mode through the DDR and OR registers. If PWMEN (resp. OVFEN) bit is set, PA3/PWM (resp. PA2/OVF) pin must be configured as output through the DDR and OR registers to be used as PWM (OVF) output of the ARTimer16. All output modes are available. PA4/CP1 or PA5/CP2 pins must be configured as input through DDR register to allow CP1 or CP2 triggered input capture of the ARTimer16. All input modes are available and I/O’s can be read inde- pendantly of the ARTimer at any time. As long as RLDSEL2, RLDSEL1 bits do not enable CP1 or CP2 triggered capture, PA4/CP1 and PA5/CP2 are standard I/O’s configurable through DDR and OR registers. 4.1.4 SPI alternate functions PD2/Sin and PD1/Scl pins must be configured as input through the DDR and OR registers to be used as data in and data clock (Slave mode) for the SPI. All input modes are available and I/O’s can be read independantly of the SPI at any time. PD3/Sout must be configured in open drain output mode to be used as data out for the SPI. In output mode, the value present on the pin is the port data register content only if PD3 is defined as push pull output, while serial transmission is possible only in open drain mode. 4.1.5 UART alternate functions PD4/RXD1 pin must be configured as input through the DDR and OR registers to be used as reception line for the UART. All input modes are available and PD4 can be read independantly of the UART at any time. PD5/TXD1 pin must be configured as output through the DDR and OR registers to be used as transmission line for the UART. Value present on the pin in output mode is the Data register content as long as no transmission is active. 35 |
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