ST62T35B datasheet(46/82 Pages) STMICROELECTRONICS

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ST62T35B/E35B

4.3.3 TIMINGS MEASUREMENT MODES

These modes are based on the capture of the

down counter content into either CP or RLCP reg-

isters. Some are used in conjunction with a syn-

chronisation of the down counter by reload func-

tions on external event on CPi pins or software

RUNRES setting, while other modes do not affect

the downcounting. As long as RELOAD bit is

cleared, the down counter remains in free running

mode.

4.3.3.1 Timing

measurement

with

startup

control

Three startup conditions, selected by RLDSELi bit

can reload the counter from RLCP and initiate the

down counting when RELOAD bit is set. The first

mode is software controlled through the RUNRES

bit, while the two others are based on external event

on pins CP1 and CP2 with configurable polarities.

External event on CP2 pin (with configurable po-

larities) is used as strobe to launch the capture of

the CT counter into CP. When RELOAD bit is set,

RLCP cannot be used for capture, since it con-

tains the reload value..

Finally, 3 different Reload/Capture sequences are

available:

– CP1 triggered restart mode with CP2 event de-

tection.

– CP2 triggered restart mode with second CP2

event detection.

– Software triggered restart mode with CP2 event

detection.

CP1 triggered restart mode with CP2 event de-

tection.

This mode is enabled for RLDSEL2=0 and

RLDSEL1=1.

External events on CPi pins are enabled as soon as

RUNRES bit is set, which lets the prescaler and the

down counter running. The next active edge on CP1

causes the counter to be loaded from RLCP, the

CP1FLG to be set and the downcounting startsfrom

RLCP value. Each following active edge on CP1 will

cause a reload of the counter. If CP1FLG is not re-

set before the next reload, the CP1ERR flag is set

at the same time as the counter is reloaded. Both

flags should then be cleared by software.

While the counter is counting, any active edge on

CP2 will capture the value of the counter at that in-

stant into the CP Register and set the CP2FLG bit.

If CP2FLG is not cleared before the following CP2

event, the CP2ERR flag bit is set, and no new cap-

ture can be performed

Capturing is re-enabled by clearing both CP2FLG

and CP2ERR.

If a capture on CP2 and a reload on CP1 occur at the

same time, the capture of the counter to CP is made

first, and then the counter is reloaded from RLCP.

Figure 26. . CP1 Triggered Restart Mode with CP2 Event Detection

RELOAD

Reload on CP1,CP2, RUNRES / Capture CP2

Capture CP1 / Capture CP2

VR02007

COUNTER

CP1

Set CP1FLG

Set CP1ERR

0000h

Disabled

Enable the Inputs

RUNRES

Software Reset

Reload and Start

Reload

Set CP1FLG

Disabled

Set CP2ERR

Disabled

Capture CT into CP

Set CP2FLG

CP2

Disabled

First Capture in CP

Then Reload

Set CP1ERR, CP2FLG

Clear all Flags

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