ST72589BW datasheet(71/158 Pages) STMICROELECTRONICS

71 / 158 page

ST72589BW, ST72389BW

71/158

PWM/BRM GENERATOR (Cont’d)

Figure 47. Precision for PWM/BRM Tuning for VOUTEFF (After filtering)

7.4.4 Register Description

On a channel basis, the 10 bits are separated into

two data registers:

Note: The number of PWM and BRM channels

available depends on the device. Refer to the de-

vice pin description and register map.

PULSE BINARY WEIGHT REGISTERS (PWMi)

Read / Write

Reset Value 1000 0000 (80h)

Bit 7 = Reserved (Forced by hardware to “1”)

Bit 6 = POL

Polarity Bit for channel i.

0: The channel

i outputs a “1” level during the bina-

ry pulse and a “0” level after.

1: The channel

i outputs a “0” level during the bina-

ry pulse and a “1” level after.

Bit 5:0 = P[5:0]

PWM Pulse Binary Weight for

channel i.

This register contains the binary value of the pulse.

BRM REGISTERS

Read / Write

Reset Value: 0000 0000 (00h)

These registers define the intervals where an in-

cremental pulse is added to the beginning of the

original PWM pulse. Two BRM channel values

share the same register.

Bit 7:4 = B[7:4]

BRM Bits (channel i+1).

Bit 3:0 = B[3:0]

BRM Bits (channel i)

Note: From the programmer's point of view, the

PWM and BRM registers can be regarded as be-

ing combined to give one data value.

For example

Effective (with external RC filtering) DAC value

POL

PPP

POL

PPPPP

PBBBB

ST72589BW 数据表(PDF) 71 Page - STMicroelectronics

ST72589BW 数据表(HTML) 71 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载