ST72589BW datasheet(44/158 Pages) STMICROELECTRONICS

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ST72589BW, ST72389BW

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LCD DRIVER (Cont’d)

7.1.4 Register Description

LCD CONTROL REGISTER (CR)

Read /Write

Reset Value: 0000 0000 (00h)

Bit 7 = DCS

Duty cycle selection

This bit is set and cleared by software.

0: 1/4 duty cycle selected

1: 1/8 duty cycle selected

Bit 6 = Reserved, always read as 0.

Bit 5:4 = CD1,CD0

Clock divider

These bits allow to tune the fLCDin frequency to

~16KHz based on the selected fCPU.

These bits are set and cleared by software.

Bit 3 = LCDE

LCD enable

This bit is set and cleared by software.

0: LCD disable

1: LCD enable

While the LCD is disabled (LCDE bit cleared),

GLCD is applied to all Segment and Common

pins.

Bit 2 = Reserved, must be kept cleared.

Bit 1:0 = FS1,FS0

fFR Frame Frequency selection

These two bits allow to select the LCD frame fre-

quency based on the fLCDin frequency and the se-

lected duty cycle.

These bits are set and cleared by software.

The following table gives the possible LCD seg-

ment frequency (fLCD) and LCD frame frequency

(fFR) according to the selected duty cycle.

With fLCDin=15625Hz (main oscillator)

DCS

CD1

CD0

LCDE

FS1

FS0

fLCDin

fCPU

Divider

CD1

CD0

15625Hz

8-MHz

1/512

4-MHz

1/256

2-MHz

1/128

1-MHz

1/64

fLCDin

Ratio

fLCD

fFR

FS1

FS0

1/4 d.c.

1/8 d.c.

1/8

1953-Hz

488-Hz

244-Hz

1/16

977-Hz

244-Hz

122-Hz

1/24

651-Hz

163-Hz

81-Hz

1/32

488-Hz

122-Hz

61-Hz

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