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ST72589BW 数据表(PDF) 27 Page - STMicroelectronics |
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ST72589BW 数据表(HTML) 27 Page - STMicroelectronics |
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27 / 158 page  ST72589BW, ST72389BW 27/158 INTERRUPTS (Cont’d) Table 6. Dedicated Interrupt Instruction Set Note: During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI instructions change the current software priority up to the next IRET instruction or one of the previously mentioned instructions. In order not to lose the current software priority level, the RIM, SIM, HALT, WFI and POP CC instructions should never be used in an interrupt routine. Table 7. Interrupt Mapping Instruction New Description Function/Example I1 H I0 N Z C HALT Entering Halt mode 1 0 IRET Interrupt routine return Pop CC, A, X, PC I1 H I0 N Z C JRM Jump if I1:0=11 I1:0=11 ? JRNM Jump if I1:0<>11 I1:0<>11 ? POP CC Pop CC from the Stack Mem => CC I1 H I0 N Z C RIM Enable interrupt (level 0 set) Load 10 in I1:0 of CC 1 0 SIM Disable interrupt (level 3 set) Load 11 in I1:0 of CC 1 1 TRAP Software trap Software NMI 1 1 WFI Wait for interrupt 1 0 N° Source Block Description Register Label Priority Order Exit from HALT Address Vector RESET Reset N/A Highest Priority Lowest Priority yes FFFEh-FFFFh TRAP Software Interrupt no FFFCh-FFFDh 0 NMI External Non Maskable Interrupt MISCR1 yes FFFAh-FFFBh 1 EI1 External Interrupt Port A3..0 N/A FFF8h-FFF9h 2 EI2 External Interrupt Port A7..4 FFF6h-FFF7h 3 EI3 External Interrupt Port B6..0 FFF4h-FFF5h 4 EI4 External Interrupt Port C7..0 FFF2h-FFF3h 5 EI5 External Interrupt Port D7..0 FFF0h-FFF1h 6 MCC Main Oscillator Time Base Interrupt MCCSR FFEEh-FFEFh 7 Not used FFECh-FFEDh 8 CAN* CAN Peripheral Interrupts CANISR FFEAh-FFEBh 9 SPI SPI Peripheral Interrupts SPISR no FFE8h-FFE9h 10 TIMER A TIMER A Peripheral Interrupts TASR FFE6h-FFE7h 11 TIMER B TIMER B Peripheral Interrupts TBSR FFE4h-FFE5h 12 SCIP SCI Peripheral Interrupts SCISR FFE2h-FFE3h 13 I2C* I2C Peripheral Interrupts I2CSRx FFE0h-FFE1h |
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