ST72589BW datasheet(18/158 Pages) STMICROELECTRONICS

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ST72589BW, ST72389BW

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RESET MANAGER (Cont’d)

3.1.3 Internal Watchdog RESET

The RESET sequence generated by a internal

Watchdog counter underflow is reduced to 2 phas-

es (see Figure 9).

Figure 9. Watchdog RESET Sequence

3.1.4 Reset Operation

The duration of the Reset condition, which is also

reflected on the output pin, is fixed at 4096 internal

CPU Clock cycles. A Reset signal originating from

an external source must have a duration of at least

1.5 internal CPU Clock cycles in order to be recog-

nised. At the end of the Power-On Reset cycle, the

MCU may be held in the Reset condition by an Ex-

ternal Reset signal. The RESET pin may thus be

used to ensure VDD has risen to a point where the

MCU can operate correctly before the User pro-

gram is run. Following a Reset event, or after exit-

ing Halt mode, a 4096 CPU Clock cycle delay pe-

riod is initiated in order to allow the oscillator to

stabilise and to ensure that recovery has taken

place from the Reset state.

During the Reset cycle, the device Reset pin acts

as an output that is pulsed low. In its high state, an

internal pull-up resistor is connected to the Reset

pin. This resistor can be pulled low by external cir-

cuitry to reset the device.

3.1.5 Power-on Reset

This circuit detects the ramping up of VDD, and

generates a pulse that is used to reset the applica-

tion at VPOR supply voltage.

Power-On Reset is designed exclusively to cope

with power-up conditions, and should not be used

in order to attempt to detect a drop in the power

supply voltage.

Caution: to re-initialize the Power-On Reset, the

power supply voltage must fall below VTN, prior to

rise above VPOR. If this condition is not respected,

on subsequent power-up the Reset pulse may not

be generated. An external Reset pulse may be re-

quired to correctly reactivate the circuit.

RESET

RUN

INTERNAL RESET

4096 CLOCK CYCLES

FETCH

VECTOR

RUN

RESET PIN

EXTERNAL RESET SOURCE

WATCHDOG RESET

WATCHDOG UNDERFLOW

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