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ST72589BW 数据表(PDF) 43 Page - STMicroelectronics |
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ST72589BW 数据表(HTML) 43 Page - STMicroelectronics |
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43 / 158 page  ST72589BW, ST72389BW 43/158 LCD DRIVER (Cont’d) 7.1.3 Segment and Common Output signals Each dot of the LCD dot matrix panel is turned on when the differential voltage between the segment signal and the common signal increases over a certain threshold, it is turned off when the voltage is below the threshold voltage. The common sig- nals determine the select timing within a frame cy- cle (see Figure 27). The common signals have similar waveforms to the segments, but different phases. Figure 27. Waveforms on LCD Outputs Each common signal shows a high signal ampli- tude (VLCD-VSS) only at the corresponding sec- tion of a frame time. At the other sections of the frame, the signal amplitude is low (3/4VLCD-1/ 4VLCD). A dot can be turned-on only at phases with high signal amplitude. In 1/8 duty cycle mode, one frame is divided into 8 sections, and each section is divided into two phases, phase 0 and 1. In 1/4 duty cycle mode, the number of sections is reduced to 4. This means the waveform pattern repeats faster in 1/4 duty cycle mode than 1/8 mode and the average voltage and the ON/OFF duty cycle on a selected pin is higher than in 1/8 mode. This results in a bet- ter contrast of the display. Note: The LCD must be disabled before entering HALT mode or ACTIVE HALT mode. Figure 28. LCD outputs with 1/8 Multiplex VLCD 3/4 1/2 1/4 GND 01 01 Common selected VLCD 3/4 1/2 1/4 GND 010 1 Common off VLCD 3/4 1/2 1/4 GND 0 101 Segment selected VLCD 3/4 1/2 1/4 GND 01 01 Segment off VLCD 3/4 1/2 1/4 GND COM8 VLCD 3/4 1/2 1/4 GND COM7 VLCD 3/4 1/2 1/4 GND SEG1 VLCD 3/4 1/2 1/4 GND SEG2 8 76 5 2 1 8 ONE FRAME PERIOD COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 0 101 0101 01 0101 |
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