ST72589BW datasheet(20/158 Pages) STMICROELECTRONICS

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ST72589BW, ST72389BW

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3.3 MAIN CLOCK CONTROLLER (MCC)

The MCC block supplies the clock for the ST7

CPU and its internal peripherals. It allows to man-

age the power saving modes such as the SLOW

and ACTIVE-HALT modes. The whole functionali-

ty is managed by the Main Clock Control/Status

ter 2 (MISCR2).

The MCC block described in Figure 12 consists of:

– a programmable CPU clock prescaler

– a time base counter with interrupt capability

– a clock-out signal to supply external devices

The prescaler allows to select the main clock fre-

quency and is controlled with three bits of the

MCCSR: CP1, CP0 and SMS.

The counter allows to generate an interrupt based

on a accurate real time clock. Four different time

bases depending directly on fOSC are available.

The whole functionality is controlled by four bits of

the MCCSR register: TB1, TB0, OIE and OIF.

The clock-out capability allows to configure a ded-

icated I/O port pin as an fOSC/2 clock out to drive

external devices. It is controlled by a bit in the

MISCR2 register: MCO.

Figure 12. Main Clock Controller (MCC) Block Diagram

DIV 2, 4, 8, 16

MCC INTERRUPT

DIV 2

TB1

TB0

OIE

OIF

CPU CLOCK

MISCR2

PROGRAMMABLE

DIVIDER

CAN

TO CPU AND

PERIPHERALS

PERIPHERAL

fOSC

fCPU

MCO

PORT

FUNCTION

ALTERNATE

OSC1

OSC2

MAIN

OSCILLATOR

MCO

CP0

CP1

SMS

MCCSR

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