ST7263B datasheet(73/132 Pages) STMICROELECTRONICS

73 / 132 page

ST7263B

73/132

USB INTERFACE (Cont’d)

11.4.5 Programming Considerations

The interaction between the USB interface and the

application program is described below. Apart

from system reset, action is always initiated by the

USB interface, driven by one of the USB events

associated with the Interrupt Status Register (IS-

TR) bits.

11.4.5.1 Initializing the Registers

At system reset, the software must initialize all reg-

isters to enable the USB interface to properly gen-

erate interrupts and DMA requests.

1. Initialize the DMAR, IDR, and IMR registers

(choice of enabled interrupts, address of DMA

buffers). Refer the paragraph titled initializing

the DMA Buffers.

2. Initialize the EP0RA and EP0RB registers to

enable accesses to address 0 and endpoint 0

to support USB enumeration. Refer to the para-

graph titled Endpoint Initialization.

3. When addresses are received through this

channel, update the content of the DADDR.

4. If needed, write the endpoint numbers in the EA

fields in the EP1RB and EP2RB register.

11.4.5.2 Initializing DMA buffers

The DMA buffers are a contiguous zone of memo-

ry whose maximum size is 48 bytes. They can be

placed anywhere in the memory space to enable

the reception of messages. The 10 most signifi-

cant bits of the start of this memory area are spec-

ified by bits DA15-DA6 in registers DMAR and

IDR, the remaining bits are 0. The memory map is

shown in Figure 38.

Each buffer is filled starting from the bottom (last 3

address bits=000) up.

11.4.5.3 Endpoint Initialization

To be ready to receive:

Set STAT_RX to VALID (11b) in EP0RB to enable

reception.

To be ready to transmit:

1. Write the data in the DMA transmit buffer.

2. In register EPnRA, specify the number of bytes

to be transmitted in the TBC field

3. Enable the endpoint by setting the STAT_TX

bits to VALID (11b) in EPnRA.

Note: Once transmission and/or reception are en-

abled, registers EPnRA and/or EPnRB (respec-

tively) must not be modified by software, as the

hardware can change their value on the fly.

When the operation is completed, they can be ac-

cessed again to enable a new operation.

11.4.5.4 Interrupt Handling

Start of Frame (SOF)

The interrupt service routine may monitor the SOF

events for a 1 ms synchronization event to the

USB bus. This interrupt is generated at the end of

a resume sequence and can also be used to de-

tect this event.

USB Reset (RESET)

When this event occurs, the DADDR register is re-

set, and communication is disabled in all endpoint

registers (the USB interface will not respond to any

packet). Software is responsible for reenabling

endpoint 0 within 10 ms of the end of reset. To do

this, set the STAT_RX bits in the EP0RB register

to VALID.

Suspend (SUSP)

The CPU is warned about the lack of bus activity

for more than 3 ms, which is a suspend request.

The software should set the USB interface to sus-

pend mode and execute an ST7 HALT instruction

to meet the USB-specified power constraints.

End Suspend (ESUSP)

The CPU is alerted by activity on the USB, which

causes an ESUSP interrupt. The ST7 automatical-

ly terminates HALT mode.

Correct Transfer (CTR)

1. When this event occurs, the hardware automat-

ically sets the STAT_TX or STAT_RX to NAK.

Note: Every valid endpoint is NAKed until soft-

ware clears the CTR bit in the ISTR register,

independently

the

endpoint

number

addressed by the transfer which generated the

CTR interrupt.

Note: If the event triggering the CTR interrupt is

a SETUP transaction, both STAT_TX and

STAT_RX are set to NAK.

2. Read the PIDR to obtain the token and the IDR

to get the endpoint number related to the last

transfer.

Note: When a CTR interrupt occurs, the TP3-

TP2 bits in the PIDR register and EP1-EP0 bits

in the IDR register stay unchanged until the

CTR bit in the ISTR register is cleared.

3. Clear the CTR bit in the ISTR register.

ST7263B 数据表(PDF) 73 Page - STMicroelectronics

ST7263B 数据表(HTML) 73 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载