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数据搜索系统，热门电子元器件搜索 |
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ST7263B 数据表(PDF) 35 Page - STMicroelectronics |
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ST7263B 数据表(HTML) 35 Page - STMicroelectronics |
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35 / 132 page  ST7263B 35/132 WATCHDOG TIMER (Cont’d) 11.1.8 Register Description CONTROL REGISTER (CR) Read /Write Reset Value: 0111 1111 (7F h) Bit 7 = WDGA Activation bit. This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset. 0: Watchdog disabled 1: Watchdog enabled Bit 6:0 = T[6:0] 7-bit timer (MSB to LSB). These bits contain the decremented value. A reset is produced when it rolls over from 40h to 3Fh (T6 becomes cleared). Table 15. Watchdog Timer Register Map and Reset Values 70 WDGA T6 T5 T4 T3 T2 T1 T0 Address (Hex.) Register Label 76 5 4 32 10 0Ch WDGCR Reset Value WDGA 0 T6 1 T5 1 T4 1 T3 1 T2 1 T1 1 T0 1 |
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