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ST7263B 数据表(PDF) 9 Page - STMicroelectronics |
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ST7263B 数据表(HTML) 9 Page - STMicroelectronics |
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9 / 132 page  ST7263B 9/132 Table 4. Hardware Register Memory Map Address Block Register Label Register name Reset Status Remarks 0000h 0001h Port A PADR PADDR Port A Data Register Port A Data Direction Register 00h 00h R/W R/W 0002h 0003h Port B PBDR PBDDR Port B Data Register Port B Data Direction Register 00h 00h R/W R/W 0004h 0005h Port C PCDR PCDDR Port C Data Register Port C Data Direction Register 1111 x000b 1111 x000b R/W R/W 0006h 0007h Reserved (2 Bytes) 0008h ITC ITIFRE Interrupt Register 00h R/W 0009h MISC MISCR Miscellaneous Register 00h R/W 000Ah 000Bh ADC ADCDR ADCCSR ADC Data Register ADC control Status register 00h 00h Read only R/W 000Ch WDG WDGCR Watchdog Control Register 7Fh R/W 000Dh to 0010h Reserved (4 bytes) 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh TIM TCR2 TCR1 TSR TIC1HR TIC1LR TOC1HR TOC1LR TCHR TCLR TACHR TACLR TIC2HR TIC2LR TOC2HR TOC2LR Timer Control Register 2 Timer Control Register 1 Timer Status Register Timer Input Capture High Register 1 Timer Input Capture Low Register 1 Timer Output Compare High Register 1 Timer Output Compare Low Register 1 Timer Counter High Register Timer Counter Low Register Timer Alternate Counter High Register Timer Alternate Counter Low Register Timer Input Capture High Register 2 Timer Input Capture Low Register 2 Timer Output Compare High Register 2 Timer Output Compare Low Register 2 00h 00h 00h xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h R/W R/W Read only Read only Read only R/W R/W Read only R/W Read only R/W Read only Read only R/W R/W 0020h 0021h 0022h 0023h 0024h SCI 1) SCISR SCIDR SCIBRR SCICR1 SCICR2 SCI Status Register SCI Data Register SCI Baud Rate Register SCI Control Register 1 SCI Control Register 2 C0h xxh 00h x000 0000b 00h Read only R/W R/W R/W R/W |
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