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ST7263B 数据表(PDF) 101 Page - STMicroelectronics |
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ST7263B 数据表(HTML) 101 Page - STMicroelectronics |
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101 / 132 page ![]() ST7263B 101/132 13.5 CLOCK AND TIMING CHARACTERISTICS Subject to general operating conditions for VDD, fCPU, and TA. 13.5.1 General Timings 1. Data based on typical application software. 2. Time measured between interrupt event and interrupt vector fetch. ∆t c(INST) is the number of tCPU cycles needed to finish the current instruction execution. 13.5.2 CONTROL TIMING CHARACTERISTICS Note 1: The minimum period t ILIL should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 cycles. Symbol Parameter Conditions Min Typ 1) Max Unit tc(INST) Instruction cycle time fCPU=8MHz 2 3 12 tCPU 250 375 1500 ns tv(IT) Interrupt reaction time 2) tv(IT) = ∆tc(INST) + 10 tCPU fCPU=8MHz 10 22 tCPU 1.25 2.75 µs CONTROL TIMINGS Symbol Parameter Conditions Value Unit Min Typ. Max fOSC Oscillator Frequency 24 MHz fCPU Operating Frequency 8 MHz tRL External RESET Input pulse Width 1.5 tCPU tPORL Internal Power Reset Duration 514 tCPU TDOGL Watchdog or Low Voltage Reset Output Pulse Width 200 ns tDOG Watchdog Time-out fcpu = 8MHz 49152 6.144 3145728 393.216 tCPU ms tOXOV Crystal Oscillator Start-up Time 20 30 40 ms tDDR Power up rise time from VDD = 0 to 4V 100 ms |
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