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STA002 数据表(PDF) 14 Page - STMicroelectronics

部件名 STA002
功能描述  STARMANO CHANNEL DECODER
PDF  43 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STA002 数据表(HTML) 14 Page - STMicroelectronics

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2. IF INTERFACE
The Master Clock (M_CLK) is the source of all
the STA002 internal timings.
M_CLK is internally divided to drive the A/D con-
verter and to provide the clock signal for the
QPSK block.
The IF input signal, centered at 1.84MHz, is over-
sampled at a frequency Fck of M_CLK/4 or
M_CLK/2 according to STA002 presettings.
2.1 PLL
This fully integrated PLL includes the phase/fre-
quency detector, the charge pump, the filter and
the VCO.
The PLL output frequency Fck can be selected via
I
2C interface according to the PLL_INT_REG.
Reg. name: PLL_INT_REG
Internal address: 21E H
Reset Value
: 00H
Type: R/W
MSB
LSB
X
X
b5
b4
b3
b2
b1
b0
Description: PLL and INTR pin control register
1.5.5 TDM_MULTIPLEX Registers (continued)
HEX_COD
DEC_COD
REGISTER NAME
TYPE
RESET
VALUE
22EH
558
RESERVED
R
0EH
22FH
559
RESERVED
R
12H
230H
560
RESERVED
R
32H
231H
561
RESERVED
R
0CH
232H
562
RESERVED
R
1CH
233H
563
RESERVED
R
2FH
234H
564
RESERVED
R
0AH
235H
565
RESERVED
R
0BH
236H
566
RESERVED
R
2AH
237H
567
RESERVED
R
09H
23CH
568
TEST_PURPOSE
R
09H
23DH
569
TEST_PURPOSE
R
09H
237EH
570
TEST_PURPOSE
R
09H
1.5.6 TSCC_MEM Registers
HEX_COD
DEC_COD
REGISTER NAME
TYPE
RESET
VALUE
300H
768
TSCW 1 (7:0)
R
301H
769
TSCW 1 (15:8)
R
302H
770
TSCW 2 (7:0)
R
303H
771
TSCW 2 (15:8)
R
304H
772
TSCW 3 (7:0)
R
305H
773
TSCW 3 (15:8)
R
306H
774
TSCW 4 (7:0)
R
307H
775
TSCW 4 (15:8)
R
3BCH
956
TSCW 95 (7:0)
R
3BDH
957
TSCW 95 (15:8)
R
3BEH
958
TSCW 96 (7:0)
R
3BFH
959
TSCW 96 (15:8)
R
3C0H
960
TSCW ID (7:0)
R
3C1H
961
TSCW ID (15:8)
R
STA002
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