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STA002 数据表(PDF) 37 Page - STMicroelectronics |
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STA002 数据表(HTML) 37 Page - STMicroelectronics |
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37 / 43 page  SYNC FOR MFP VERIFICATION SYNC 2112 SYMBOLS DATA MULTIPLEX SCH MFP VER TSCC READ DATA READ TDM STATE MACHINE TDM SYNCHRONISATION STATE MACHINE MFP DETECTION PRE SYNC START INTERNAL TIMING 251712 SYMBOLS 96 SY TDM FRAME 138 ms SYNC TSCC VITERBI & RS DECODED TSCC AVAILABLE I2C INTERFACE BC SELECTION PRC EXTRACTION from 1 to8 PRC CHANNELS TSCC DATA MULTIPLEX MFP TSCC TSCC TSCC MFP DATA MULTIPLEX MFP DATA MULTIPLEX DATA MULTIPLEX MFP MFP DATA MULTIPLEX TSCC MFP TSCC DATA MULTIPLEX MFP DETECTION MFP TSCC TSCC FIELD TSCC FIELD TSCC FIELD TSCC FIELD TSCC FIELD TSCC FIELD MFP VER MFP VER DATA READ DATA READ DATA READ MFP VER DATA READ MFP VER DATA READ MFP VER DATA READ TSCC AVAILABLE PRCP PRCP DATA FIELD PRC FRAME 432 ms MFP LOCK PRCP DETECTION PRE SYNC SYNC ALL PRC EXTRACTED LOCK MFP LOCK DATA FIELD PRC SYNCHRONISATION STATE MACHINE DATA FIELD DATA FIELD SP SP DATA FIELD DATA FIELD PROTECTED BC FRAME 432 ms PRC CHANNELS MULTIPEXING DATA FIELD DATA FIELD SP SP VITERBI & RS & DEINTELEAVER DECODED BC FRAME 432 ms Tdec Ty Tx SP DETECTION PRE SYNC SP DETECTION SYNC MFP TSCC TDM SYNCHRONISATION STATE MACHINE CASE 1 NORMAL SYNC CASE 2 HW SYNC SP LOCK SP LOCK BC FRAME SYNC Ta FRAME SYNCRONIZATION 8.4 FRAME SYNCRONIZATION TIMES Tx = MFP detection time: 0 to 138ms Ta = TSCC decodification time:= < 2ms Ty = PRCP detection time: 0 to 432ms Tdec = VITERBI decoding + REED SOLOMON error correction + deinterleaving: ~55ms x PRC number TDM SYNCRONIZATION TIME TDM lock = QPSK lock + Tx + 138ms PRC SYNCRONIZATION TIME PRC lock = QPSK lock +TDM lock + Ty + 432 ms BC SYNCRONIZATION TIME CASE 1 ( SW sync): the BC synchronization FSM asserts the lock sig- nal when the SP is detected two consecutive times. BC lock = QPSK lock + TDM lock + Ty + Tdec + 432 ms CASE 2 ( HW sync): the BC synchronization FSM asserts the lock sig- nal when the BC FRAME SYNC signal is as- serted by the PRC alignment FSM and the SP is valid. BC lock = QPSK lock + TDM lock + Ty + Tdec Note : About the BC synchronisation, the selection be- tween SW sync and HW syn is achievable through the register BC_ALARM add 01CH bit b5. Bit b5 = 1 indicates the SW sync Bit b5 = 0 indi- cates HW sync. STA002 37/43 |
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