STA002 datasheet(35/43 Pages) STMICROELECTRONICS

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8. GENERAL INFORMATION

8.1 DECRIPTION

The STA002 supports a crypto-scheme named

WES (World Space Encrypton Scheme)

It is composed of two functional blocks:

- CSG (Crypto Sequence Generator)

implemented in the STA002 decoder

- IWG (Initialization Word Generator) processed

by external hardware such as a microcontroller

or a smart card.

The CSG module produces the pseudo-casual

sequence by an algorithm based on the galois ar-

rithmetic.

This algorithm is derived in 2 phases:

1) Key expansion

2) Pseudo casual sequence generation

In the expansion phase activated every frame the

IWG 8 bytes key is used to initialize a 16 bytes

array.

The scrambling procedure, invoked every byte,

implements a pseudo random algorithm.

The XOR operation between the output of the

module the encrypted bytes completes the de-

cryption procedure.

The 8 bytes keyword is loaded before the start of

the new frame to the I

2C bus interface.

8.2. BROADCAST CHANNEL INTERFACE

The Broadcast Channel interface consists of 4

wires: output clock (BCCK), output BC data

(BCDO), output BC frame sync. (BCSYNC) and

input BC data (BCDIN).

The data trasmitted and recived via the broadcast

channel interface are 8 bit bursts.

The most significant bit is transmitted first.

Fig.7 shows the broadcast channel serial data out

(BCDO) burst of 8 bit (MSB first). The data bits

are valid at the negative slope of the clock line

(BCCK).

The BCSYNC signal indicates the first byte of the

broadcast channel Service preamble (04H) allow-

ing an easy syncronization to external modules

using the BC data.

The input BC line (BCDI) must have the same

format of the BC output (BCDO). The data bit

must be valid on the negative edge of the output

clock line (BCCK).

The maximum delay allowed from the output data

and the input data is 4 bytes (4 bursts of 8 bits).

The input delay is programmable via I2C bus with

the BCIN_DELAY_REG register (01BH).

8.3 SERVICE COMPONENT INTERFACES

The STA002 provides two service component in-

terfaces which support the same protocol:

- SC DATA INTERFACE (SCEN, SCDO, SCCK)

- SOURCE DECODER INTERFACE (SEN, SDO, SCK)

The service component interfaces consists of 3

wires each. Output clock (SCCK/SCK), SC data

(SCDO/SDO) and SC byte sync (SCEN/SEN).

The data transmitted via the service component

interface are 8 bit bursts.

The most significant bit is transmitted first.

As shown in fig.8 the service component serial

data out (SCDO/SDO) combines burst of 8 bit

length (MSB first). The data bit are valid at the

negative edge of the clock line (SCCK/ SCK).

The slope change of the SCEN/SEN indicates the

most significative bit of the 8 bit service compo-

nent burst.

The SCEN/SEN signal is used if required for the

data bits alignement only.

76543210

tclk

tclk-off

76543210

XYAB

PROGRAMMABLE DELAY FROM BC-OUT DATA

TO BC-IN DATA MAX 4 BYTE

D97AU744A

tclk-off < 1.2ms

tclk ~ 6.5µs

BCCK

BCDO

BCSYNC

BCDI

Fig. 7: Format Of The Broadcast Channel Interface (BC)

STA002

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