STA002 datasheet(15/43 Pages) STMICROELECTRONICS

15 / 43 page

PLL output clock (ADC input)

M_CLK (pin 9)

2XM_CLK (pin9)

Test purpose

INTR pin control

Normal function (from ERROR_REG)

BC_LOCK signal on INTR pin

MFP_LOCK signal on INTR pin

PRCP_ALL_LOCK on INTR pin

b3, b2: Test purpose

2.2 A/D CONVERTER

This block performs the analog to digital conver-

sion of the incoming IF input signal.

The ADC has a resolution of 6 bit and is based

on the so called Half Flash architecture to reduce

both area and power consumption.

The sampling rate depends on the M_CLK (Mas-

ter Clock) frequency and on the PLL presetting.

3. QPSK DEMODULATOR

3.1 QUADRATURE DEMODULATOR

The final base-band demodulation is performed in

this block.

The samples of the IF input signal are multiplied

by the sine and cosine functions to get the two in-

phase (I) and quadrature (Q) components of the

QPSK signal. The phase ambiguity inherent in

QPSK is solved in the frame synchronisation part.

A programmable bit allows to multiply by -1 the

quadrature component in order to accomodate

QPSK modulation with another convention of ro-

tation sense (this is equivalent to a permutation of

I and Q components).

The sine and cosine functions are generated by

an NCO using a phase accumulator and a look-

up table.

3.2. INTERPOLATOR NYQUIST FILTER

The I and Q components are filtered by a digital

Nyquist root filter with the following features:

Separate I and Q stream, Fck/Fsym samples per

symbols;

Raised root cosine shape with roll-off factor of

40%;

Separate I and Q output stream, 1 sample per

symbol.

This filter performs both the Nyquist filter function

(matched with the one in the transmission side)

and the interpolation function to compute the opti-

mum output sample.

3.3. TIMING RECOVERY

The timing loop is completely implemented digi-

tally and comprises the timing detector working at

symbol rate, a loop filter, the timing NCO and the

Nyquist/interpolator filters.

The loop is controlled by two parameters, al-

pha_tmg

and

beta_tmg

contained

the

TIMFLTPAR register.

3.3.1 Timing loop registers

Timing

loop

filter

parameter

(TIMFLTPAR)

Internal address: 8D H

Reset Value: 48H

MSB

LSB

alpha_tmg

beta_tmg

Timing frequency registers (TIMINTG)

Internal address: 8E H

Reset Value: 0AH

MSB

LSB

signed number

The value of this register, when the system is

locked, is an image of the frequency offset.

Timing NCO frequency setting (SYMFREQ)

Internal address: 8C H 8B H 8A H

Reset Value

: 0CH 11H D3H

MSB

LSB

b23

b22

b21

b20

b19

b18

b17

b16

SYMFREQ3

MSB

LSB

b15

b14

b13

b12

b11

b10

SYMFREQ2

MSB

LSB

SYMFREQ1

This register is divided into three bytes. The LSB

byte is named SYMFREQ1, the MSB is named

SYMFREQ3.

STA002

15/43

STA002 数据表(PDF) 15 Page - STMicroelectronics

STA002 数据表(HTML) 15 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

数据表下载