STA002 datasheet(6/43 Pages) STMICROELECTRONICS

6 / 43 page

FUNCTIONAL DESCRIPTION

The STA002 integrates all the functions needed

to demodulate the signal coming from the RF FE;

with reference to the block diagram (Fig 1),

STA002 includes the following functions:

Microprocessor interface

Data transmission from microcontroller to the de-

vice takes place through the 2 wires (SDA and

SCL) I2C bus interface. STA002 acts always as a

slave in all its communications.

Interface to the Front-end

This block receives from the RF front-end the

QPSK modulated signal, centered at 1.84 MHz

(2nd IF frequency). This signal is over sampled

using the Master Clock and converted to digital

on 6 bits in 2’s complement format. The same fre-

quency is also used to provide the clock signal for

the QPSK demodulator block.

QPSK

This block is composed by:

- AGC1

- quadrature demodulator

- carrier recovery

- timing recovery

- frequency sweep generator

- AGC2

- lock indicator

- carrier to noise estimator

To assure flexibility and to cover different working

conditions most of the parameters of each func-

tion can be programmed through the I2C inter-

face.

TDM Demultiplexer

The TDM frame is divided into 3 fields.

The first is the Master Frame Preamble (MFP)

which contains the synchronisation word. The

second, the Time Slot Control Channel (TSCC),

contains information about the organization of the

Prime Rate Channel data which follows. The

third, is the data field; it contains 96 Prime Rate

Channels of 16 Kbit/s each; up to 8 Prime Rate

Channels are grouped into one Broadcast Chan-

nel.

The TDM demultiplexer executes the extraction

and decoding of one Broadcast Channel from the

TDM stream, according to the instructions com-

ing from the microcontroller. The decoding flow is

the following:

- TDM synchronization

The master frame synchronization block receives

the demodulated symbol stream from the QPSK

demodulator and performs the alignment detect-

ing the Master Frame Preamble.

The known syncronization word is also used to

correct the phase ambiguity intrinsic in QPSK de-

modulation.

- TSCC extraction

The information of the Prime Rate Channels to

Broadcast Channels allocation are contained in

the TSCC field which is synchronised with the

MFP.

In this stage all the information related to the

TSCC are extracted and made available for the

microcontroller via the I2C interface.

- PRC extraction and BC recovery

This block, after the Broadcast Channel (BC) se-

lection, performs the extraction and synchronisa-

tion of the Prime Rate Channels (PRC) belonging

to the selected BC.

The extracted PRCs are aligned and grouped into

one BC data stream.

- FEC decoder

The extracted BC is decoded using a concate-

nated Forward Error Correction approach.

The FEC circuitry utilizes three error correction

stages: a rate 1/2 Viterbi decoder, a 255x4 bytes

convolutional deinterleaver and a 255/223 Reed

Solomon decoder.

The RS input blocks are 255 bytes long with 32

parity bytes.

Up to 16 errored bytes can be fixed in each RS

block.

BC demultiplexer

Every BC contains up to 8 Service Components;

the Service Control Header (SCH) field contains

all the information related to the organization of

the Service Components. This stage provides the

extraction of the SCH from the BC.

The SCH is available through I2C bus to the mi-

crocontroller for the selection of the desired Audio

Service Component, which is then supplied di-

rectly to the MPEG Source decoder via the audio

Service Component Interface.

DEVICE OPERATION

1. I

2C BUS SPECIFICATION

The STA002 supports the I2C protocol. This pro-

tocol defines any device that sends data on to the

bus as a transmitter and any device that reads

the data as a receiver. The device that controls

the data transfer is known as the master and the

others as the slave. The master will always initi-

ate the transfer and will provide the serial clock

STA002

6/43

STA002 数据表(PDF) 6 Page - STMicroelectronics

STA002 数据表(HTML) 6 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

数据表下载