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ADE7569 数据表(PDF) 46 Page - Analog Devices |
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ADE7569 数据表(HTML) 46 Page - Analog Devices |
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46 / 136 page ![]() ADE7566/ADE7569 Preliminary Technical Data Rev. PrA | Page 46 of 136 POWER QUALITY MEASUREMENTS Zero-Crossing Detection Each ADE7566/ADE7569 has a zero-crossing detection circuit on the voltage channel. This zero crossing is used to produce an external zero-crossing signal (ZX) and is used in calibration mode. The zero-crossing is generated by default from the output of LPF1. This filter has a low cut-off frequency and is intended for 50 Hz and 60 Hz systems. If needed, this filter can be disabled to allow a higher frequency signal to be detected or to limit the group delay of the detection. If the voltage input fundamental frequency is below 60 Hz, and a time delay in ZX detection is acceptable, it is recommended to enable LPF1. Enabling LPF1 limits the variability in the ZX detection by eliminating the high frequency components. Figure 42 shows how the zero-crossing signal is generated. ×1, ×2, ×4, ×8, ×16 ADC 2 REFERENCE LPF1 f–3dB = 63.7Hz PGA2 {GAIN [7:5]} VP VN V2 ZERO CROSS ZX HPF MODE1[6] 43.24° @ 60Hz 1.0 0.73 ZX V2 LPF1 Figure 42. Zero-Crossing Detection on Voltage Channel The zero-crossing signal ZX is generated from the output of LPF1 (bypassed or not). LPF1 has a single pole at 63.7 Hz (at MCLK = 4.096 MHz). As a result, there is a phase lag between the analog input signal V2 and the output of LPF1. The phase lag response of LPF1 results in a time delay of approximately 2 ms (@ 60 Hz) between the zero crossing on the analog inputs of the voltage channel and ZX detection. The zero-crossing detection also drives the ZX flag in the Interrupt Status Register 3 SFR (MIRQSTH, 0xDE). If the ZX bit in the Interrupt Enable Register 3 SFR (MIRQENH, 0xDB) is set, the 8052 core has a pending ADE interrupt. The ADE interrupt stays active until the ZX status bit is cleared (see the Energy Measurement Interrupts section). Zero-Crossing Timeout The zero-crossing detection also has an associated timeout register, ZXTOUT. This unsigned, 12-bit register is decremented (1 LSB) every 160/MCLK sec. The register is reset to its user programmed, full-scale value every time a zero crossing is detected on the voltage channel. The default power-on value in this register is 0xFFF. If the internal register decrements to 0 before a zero crossing is detected in the Interrupt Status Register 3 SFR (MIRQSTH, 0xDE), and the ZXTO bit in the Interrupt Enable Register 3 SFR (MIRQENH, 0xDB) is set, the 8052 core has a pending ADE interrupt. The ADE interrupt stays active until the ZXTO status bit is cleared (see the Energy Measurement Interrupts section). The ZXOUT register (Address 0x11) can be written or read by the user (see the Energy Measurement Register List section). The resolution of the register is 160/MCLK sec per LSB. Thus, the maximum delay for an interrupt is 0.16 sec (128/MCLK × 212) when MCLK = 4.096 MHz. Figure 43 shows the mechanism of the zero-crossing timeout detection when the line voltage stays at a fixed dc level for more than CLKIN/160 × ZXTOUT sec. 12-BIT INTERNAL REGISTER VALUE ZXTOUT ZXTO FLAG BIT VOLTAGE CHANNEL Figure 43. Zero-Crossing Timeout Detection Period or Frequency Measurements The ADE7566/ADE7569 provide the period or frequency measurement of the line. The period or frequency measurement is selected by clearing or setting FREQSEL bit in the MODE2 Register (0x0C). The period/frequency register, PER_FREQ Register (0x0A), is an unsigned 16-bit register that is updated every period. If LPF1 is enabled, a settling time of 1.8 sec is associated with this filter before the measurement is stable. When the period measurement is selected, the measurement has a 2.44 μs/LSB (MCLK/10) when MCLK = 4.096 MHz, which represents 0.014% when the line frequency is 60 Hz. When the line frequency is 60 Hz, the value of the period register is approximately 0d6827. The length of the register enables the measurement of line frequencies as low as 12.5 Hz. The period register is stable at ±1 LSB when the line is established and the measurement does not change. When the frequency measurement is selected, the measurement has a 0.0625 Hz/LSB resolution when MCLK = 4.096 MHz, which represents 0.104% when the line frequency is 60 Hz. When the line frequency is 60 Hz, the value of the frequency register is 0d960. The frequency register is stable at ±4 LSB when the line is established and the measurement does not change. |
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