ADE7569 datasheet(100/136 Pages) AD

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ADE7566/ADE7569

Preliminary Technical Data

Rev. PrA | Page 100 of 136

TIMERS

Each ADE7566/ADE7569 has three 16-bit timer/counters: Timer 0,

Timer 1, and Timer 2. The timer/counter hardware is included

on-chip to relieve the processor core of overhead inherent in

implementing timer/counter functionality in software. Each

timer/counter consists of two 8-bit registers: THx and TLx

(x = 0, 1, or 2). All three can be configured to operate either as

timers or as event counters.

When functioning as a timer, the TLx register is incremented

every machine cycle. Thus, users can think of it as counting

machine cycles. Because a machine cycle on a single-cycle core

consists of one core clock period, the maximum count rate is

the core clock frequency.

When functioning as a counter, the TLx register is incremented

by a 1-to-0 transition at its corresponding external input pin:

T0, T1, or T2. When the samples show a high in one cycle and a

low in the next cycle, the count is incremented. Because it takes

two machine cycles (two core clock periods) to recognize a 1-to-0

transition, the maximum count rate is half the core clock frequency.

There are no restrictions on the duty cycle of the external input

signal, but to ensure that a given level is sampled at least once

before it changes, it must be held for a minimum of one full

machine cycle. User configuration and control of all timer

operating modes is achieved via the SFRs in Table 98.

Table 98. Timer SFRs

SFR

Address

Bit Addressable

Description

TCON

0x88

Yes

Timer0 and Timer1 Control Register (see Table 100).

TMOD

0x89

Timer0 and Timer1 Mode Register (see Table 99).

TL0

0x8A

Timer0 LSB (see Table 103).

TL1

0x8B

Timer1 LSB (see Table 105).

TH0

0x8C

Timer0 MSB (see Table 102).

TH1

0x8D

Timer1 MSB (see Table 104).

T2CON

0xC8

Yes

Timer2 Control Register (see Table 101).

RCAP2L

0xCA

Timer2 Reload/Capture LSB (see Table 109).

RCAP2H

0xCB

Timer2 Reload/Capture MSB (see Table 108).

TL2

0xCC

Timer2 LSB (see Table 107).

TH2

0xCD

Timer2 MSB (see Table 106).

TIMER SFR REGISTERS

Table 99. Timer/Counter 0 and Timer/Counter 1 Mode SFR (TMOD, 0x89)

Bit No.

Mnemonic

Default

Description

Gate1

Timer 1 Gating Control. Set by software to enable Timer/Counter 1 only when the INT1 pin is high and

the TR1 control is set. Cleared by software to enable Timer 1 whenever the TR1control bit is set.

C/T1

Timer 1 Timer or Counter Select Bit. Set by software to select counter operation (input from T1 pin).

Cleared by software to select the timer operation (input from internal system clock).

Timer 1 Mode Select Bits.

T1/M[1:0]

Result

TH1 operates as an 8-bit timer/counter. TL1 serves as 5-bit prescaler.

16-Bit Timer/Counter. TH1 and TL1 are cascaded; there is no prescaler.

8-Bit Autoreload Timer/Counter. TH1 holds a value that is to be reloaded into TL1 each

time it overflows.

5 to 4

T1/M1,

T1/M0

Timer/Counter 1 Stopped.

Gate0

Timer 0 Gating Control. Set by software to enable Timer/Counter 0 only when the INT0 pin is high and the

TR0 control bit is set. Cleared by software to enable Timer 0 whenever the TR0 control bit is set.

C/T0

Timer 0 Timer or Counter Select Bit. Set by software to the select counter operation (input from T0 pin).

Cleared by software to the select timer operation (input from internal system clock).

Timer 0 Mode Select Bits.

T0/M[1:0]

Result

TH0 operates as an 8-bit timer/counter. TL0 serves as a 5-bit prescaler.

16-Bit Timer/Counter. TH0 and TL0 are cascaded; there is no prescaler.

8-Bit Autoreload Timer/Counter. TH0 holds a value that is to be reloaded into TL0 each

time it overflows.

1 to 0

T0/M1,

T0/M0

TL0 is an 8-bit timer/counter controlled by the standard Timer 0 control bits. TH0 is an

8-bit timer only, controlled by Timer 1 control bits.

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