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ADE7569 数据表(PDF) 24 Page - Analog Devices |
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ADE7569 数据表(HTML) 24 Page - Analog Devices |
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24 / 136 page  ADE7566/ADE7569 Preliminary Technical Data Rev. PrA | Page 24 of 136 Table 15. Power Management Interrupt Flag SFR (IPSMF, 0xF8) Bit No. Address Mnemonic Default Description 7 0xFF FPSR 0 Power Supply Restored Interrupt Flag. Set when the VDD power supply has been restored. This occurs when the source of VSW changes from VBAT to VDD. 6 0xFE FPSM 0 PSM Interrupt Flag. Set when an enabled PSM interrupt condition occurs. 5 0xFD FSAG 0 Voltage SAG Interrupt Flag. Set when an ADE energy measurement SAG condition occurs. 4 0xFC RESERVED 0 This bit must be kept cleared for proper operation. 3 0xFB FVADC 0 VDCIN Monitor Interrupt Flag. Set when VDCIN changes by VDCIN_DIFF or when VDCIN measurement is ready. 2 0xFA FBAT 0 VBAT Monitor Interrupt Flag. Set when VBAT falls below BATVTH or when VBAT measurement is ready. 1 0xF9 FBSO 0 Battery Switchover Interrupt Flag. Set when VSW switches from VDD to VBAT. 0 0xF8 FVDCIN 0 VDCIN Monitor Interrupt Flag. Set when VDCIN falls below 1.2 V. Table 16. Battery Switchover Configuration SFR (BATPR, 0xF5) Bit No. Mnemonic Default Description 7 to 2 Reserved 00 These bits must be kept to 0 for proper operation. Control Bits for Battery Switchover. BATPRG[1:0] Result 00 Battery switchover enabled on low VDD 01 Battery switchover enabled on low VDD and low VDCIN 1 to 0 BATPRG[1:0] 00 1X Battery switchover disabled Table 17. Peripheral Configuration SFR (PERIPH, 0xF4) Bit No. Mnemonic Default Description 7 RXFLAG 0 If set, indicates that an Rx edge event triggered wake-up from PSM2. 6 VSWSOURCE 1 Indicates the power supply that is internally connected to VSW (0 VSW = VBAT, 1 VSW = VDD). 5 VDD_OK 1 If set, indicates that VDD power supply is ready for operation. 4 PLL_FLT 0 If set, indicates that a PLL fault occurred where the PLL lost lock. Set the PLLACK bit in the Start ADC Measurement SFR (ADCGO, 0xD8) to acknowledge the fault and clear the PLL_FLT bit. 3 REF_BAT_EN 0 If set, internal voltage reference enabled in PSM2 mode. This bit should be set if LCD is on in PSM2 mode. 2 Reserved 0 This bit should be kept to zero. Controls the function of the P1.0/RxD pin. RXPROG[1:0] Result 00 GPIO 01 RxD with wake-up disabled 1 to 0 RXPROG[1:0] 00 11 RxD with wake-up enabled Table 18. Power Management Interrupt Enable SFR (IPSME, 0xEC) Bit No. Interrupt Enable Bit Default Description 7 EPSR 0 Enables a PSM interrupt when the power supply restored flag (FPSR) is set. 6 RESERVED 0 Reserved. 5 ESAG 0 Enables a PSM interrupt when the voltage SAG flag (FSAG) is set. 4 RESERVED 0 This bit must be kept cleared for proper operation. 3 EVSW 0 Enables a PSM interrupt when the VSW monitor flag (FVSW) is set. 2 EBAT 0 Enables a PSM interrupt when the VBAT monitor flag (FBAT) is set. 1 EBSO 0 Enables a PSM interrupt when the battery switchover flag (BSFO) is set. 0 EVDCIN 0 Enables a PSM interrupt when the VDCIN monitor flag (FVDCIN) is set. |
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