ADE7569 datasheet(18/136 Pages) AD

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ADE7566/ADE7569

Preliminary Technical Data

Rev. PrA | Page 18 of 136

Pin No.

Mnemonic

Description

P0.2/CF1/RTCCAL

General-Purpose Digital I/O Port 0.2. / Calibration Frequency Logic Output. The CF1 logic output gives

instantaneous active, reactive, or apparent power information / RTC Calibration Frequency Logic Output.

The RTCCAL logic output gives access to the calibrated RTC output.

SDEN/P2.3

This pin is used to enable serial download mode through a resistor when pulled low on power-up or reset.

On reset, this pin momentarily becomes an input and the status of the pin is sampled. If there is no pull-

down resistor in place, the pin momentarily goes high and then user code is executed. If a pull-down resistor

is in place, the embedded serial download/debug kernel executes and this pin remains low during internal

program execution. / General-Purpose Digital I/O Port 2.3.

BCTRL/INT1/P0.0

Digital Input for Battery Control. This logic input connects VDD or VBAT to VSW internally when set to logic high

or low, respectively. When left open, the connection between VDD or VBAT and VSW is selected internally.

/ External Interrupt Input. / General-Purpose Digital I/O Port 0.0.

XTAL2

A crystal can be connected across this pin and XTAL1 (see XTAL1 description below) to provide a clock

source for the ADE7566/ADE7569. The XTAL2 pin can drive one CMOS load when an external clock is

supplied at XTAL1 or by the gate oscillator circuit.

XTAL1

An external clock can be provided at this logic input. Alternatively, a parallel resonant AT crystal can be

connected across XTAL1 and XTAL2 to provide a clock source for the ADE7566/ADE7569. The clock

frequency for specified operation is 32.768 kHz.

INT0

Interrupt Input.

49, 50

VP, VN

Analog Inputs for Voltage Channel. These inputs are fully differential voltage inputs with a maximum

differential level of ±500 mV for specified operation. This channel also has an internal PGA.

This pin is used as an input for emulation. When held high, this input enables the device to fetch code from

internal program memory locations. The ADE7566/ADE7569 do not support external code memory. This pin

should not be left floating.

52, 53

IP, IN

Analog Inputs for Current Channel. These inputs are fully differential voltage inputs with a maximum

differential level of ±500 mV for specified operation. This channel also has an internal PGA.

AGND

This pin provides the ground reference for the analog circuitry.

FP26

LCD Segment Output 26.

RESET

Reset Input, Active Low.

REFIN/OUT

This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of

1.2 V ± 8% and a typical temperature coefficient of 50 ppm/°C maximum. This pin should be decoupled with

a 1 μF capacitor in parallel with a ceramic 100 nF capacitor.

VBAT

3.3 V Power Supply Input from the Battery. This pin is connected internally to VDD when the battery is

selected as the power supply for the ADE7566/ADE7569.

VINTA

This pin provides access to the on-chip 2.5 V analog LDO. No external active circuitry should be connected to

this pin. This pin should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor.

VDD

3.3 V Power Supply Input from the Regulator. This pin is connected internally to VDD when the regulator is

selected as the power supply for the ADE7566/ADE7569. This pin should be decoupled with a 10 μF

capacitor in parallel with a ceramic 100 nF capacitor.

VSWOUT

3.3 V Power Supply Output. This pin provides the supply voltage for the LDOs and internal circuitry of the

ADE7566/ADE7569. This pin should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF

capacitor.

VINTD

This pin provides access to the on-chip 2.5 V digital LDO. No external active circuitry should be connected to

this pin. This pin should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor.

DGND

This pin provides the ground reference for the digital circuitry.

VDCIN

Analog Input for DC Voltage Monitoring. The maximum input voltage on this pin is 3.3 V with respect to

AGND. This pin is used to monitor the pre-regulated dc voltage.

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