ADE7569 datasheet(86/136 Pages) AD

86 / 136 page

ADE7566/ADE7569

Preliminary Technical Data

Rev. PrA | Page 86 of 136

Writing to the Watchdog Timer SFR (WDCON, 0xC0)

Writing data to the WDCON SFR involves a double instruction sequence. The WDWR bit must be set and the following instruction must

be a write instruction to the WDCON SFR.

Disable Watch dog

CLR EA

SETB WDWR

CLR WDE

SETB EA

This sequence is necessary so that the WDCON SFR is protected from code execution upsets that might unintentionally modify this SFR.

Interrupts should be disabled during this operation due to the consecutive instruction cycles.

Table 72. Watchdog and Flash Protection Byte in Flash (Flash Address = 0x3FFA)

Bit No.

Mnemonic

Default

Description

This bit holds the protection for the Watchdog timer and the 7th bit of the flash protection key.

When this bit is cleared, the watchdog enable and event, selected by WDE and WDIR cannot be

changed by user code. The watchdog configuration is then fixed to WDIR=0 and WDE=1. The

watchdog timeout in PRE[3:0] can still be modified by user code.

WDPROT_PROTKY7

The value of this bit is also used to set the Flash protection key. If this bit is cleared to protect the

watchdog, then the default value for the Flash protection key is 0x7F instead of 0xFF (see the

Protecting the Flash section for more information on how to clear this bit).

7 to 0

PROTKY[7:0]

0xFF

These bits hold the flash protection key. The content of this Flash address is compared to the

Flash Protection Key SFR (PROTKY, 0xBB) when the protection is being set or changed. If the two

values match, the new protection is written to the Flash addresses 0x3FFF to 0x3FFB. see the

Protecting the Flash section for more information on how to configure these bits.

Watchdog Timer Interrupt

If the watchdog timer is not cleared within the watchdog timeout

period, a system reset occurs unless the watchdog timer interrupt

is enabled. The watchdog timer interrupt enable bit (WDIR) is

located in the Watchdog Timer SFR (WDCON, 0xC0). Enabling

the WDIR bit allows the program to examine the stack or other

variables that may have led the program to execute inappropriate

code. The watchdog timer interrupt also allows the watchdog to

be used as a long interval timer.

Note that WDIR is automatically configured as a high priority

interrupt. This interrupt cannot be disabled by the EA bit in the

IE register. Even if all of the other interrupts are disabled, the

watchdog is kept active to watch over the program.

ADE7569 数据表(PDF) 86 Page - Analog Devices

ADE7569 数据表(HTML) 86 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载